Invention Application
- Patent Title: METHOD FOR FABRICATING SHALLOW TRENCH ISOLATION STRUCTURES USING DIBLOCK COPOLYMER PATTERNING
- Patent Title (中): 使用二嵌段共聚物图案制作浅层分离结构的方法
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Application No.: US11621124Application Date: 2007-01-09
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Publication No.: US20080164558A1Publication Date: 2008-07-10
- Inventor: Haining Yang , Wai-Kin Li
- Applicant: Haining Yang , Wai-Kin Li
- Applicant Address: US NY ARMONK
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY ARMONK
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/762

Abstract:
A method of isolating semiconductor devices formed on a semiconductor substrate having a silicon on insulator (SOI) layer is provided. The method includes forming at least one shallow trench area on a pad nitride layer deposited on a surface of the SOI layer, wherein the at least one shallow trench area includes an opening for exposing a portion of the SOI layer; applying diblock copolymer material over the pad nitride layer and the at least one shallow trench area; annealing the applied copolymer material to form self-organized patterns; and partially etching the shallow trench area using the diblock copolymer material as an etch mask. A semiconductor structures is also described having an isolation structure formed on a SOI layer of a semiconductor substrate the isolation structure having an oxidized substrate region; and a void region formed on the oxidized substrate region.
Public/Granted literature
- US07514339B2 Method for fabricating shallow trench isolation structures using diblock copolymer patterning Public/Granted day:2009-04-07
Information query
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