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    STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE
    71.
    发明申请
    STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE 有权
    半导体器件结构的结构与形成方法

    公开(公告)号：US20160365449A1

    公开(公告)日：2016-12-15

    申请号：US14827092

    申请日：2015-08-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Che-Cheng CHANG ,  Chih-Han LIN

    IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

    CPC classification number: H01L29/7851 ,  H01L21/28247 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a protection element over the gate stack. A top of the protection element is wider than a bottom of the protection element. The semiconductor device structure also includes a spacer element over a side surface of the protection element and a sidewall of the gate stack. The semiconductor device structure further includes a conductive contact electrically connected to a conductive feature over the semiconductor substrate.

    Abstract translation: 提供半导体器件结构的结构和形成方法。 半导体器件结构包括半导体衬底上的栅极堆叠以及栅堆叠上的保护元件。 保护元件的顶部比保护元件的底部宽。 半导体器件结构还包括在保护元件的侧表面上的间隔元件和栅极堆叠的侧壁。 半导体器件结构还包括电连接到半导体衬底上的导电特征的导电接触。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    73.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
    半导体器件及其制造方法

    公开(公告)号：US20160204215A1

    公开(公告)日：2016-07-14

    申请号：US14749602

    申请日：2015-06-24

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Che-Cheng CHANG ,  Chih-Han LIN

    IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L21/311 ,  H01L27/088 ,  H01L29/78

    CPC classification number: H01L29/42376 ,  H01L21/31111 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

    Abstract: A Fin FET semiconductor device includes a fin structure extending in a first direction and extending from an isolation insulating layer. The Fin FET device also includes a gate stack including a gate electrode layer, a gate dielectric layer, side wall insulating layers disposed at both sides of the gate electrode layer, and interlayer dielectric layers disposed at both sides of the side wall insulating layers. The gate stack is disposed over the isolation insulating layer, covers a portion of the fin structure, and extends in a second direction perpendicular to the first direction. A recess is formed in an upper surface of the isolation insulating layer not covered by the side wall insulating layers and the interlayer dielectric layers. At least part of the gate electrode layer and the gate dielectric layer fill the recess.

    Abstract translation: Fin FET半导体器件包括在第一方向上延伸并从隔离绝缘层延伸的翅片结构。 鳍FET器件还包括栅极堆叠，其包括栅极电极层，栅极电介质层，设置在栅电极层两侧的侧壁绝缘层，以及设置在侧壁绝缘层两侧的层间电介质层。 栅堆叠设置在隔离绝缘层上，覆盖鳍结构的一部分，并且沿垂直于第一方向的第二方向延伸。 在隔离绝缘层的未被侧壁绝缘层和层间电介质层覆盖的上表面形成凹部。 栅极电极层和栅极电介质层的至少一部分填充凹部。

    SEMICONDUCTOR DEVICE
    76.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220367719A1

    公开(公告)日：2022-11-17

    申请号：US17875152

    申请日：2022-07-27

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Che-Cheng CHANG ,  Chih-Han LIN

    IPC: H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

    Abstract: A device includes a substrate, a shallow trench isolation (STI) structure, an isolation structure, and a gate stack. The substrate has a semiconductor fin. The shallow trench isolation (STI) structure is over the substrate and laterally surrounding the semiconductor fin. The isolation structure is disposed on a top surface of the STI structure. The gate stack crosses the semiconductor fin, over the STI structure, and in contact with a sidewall the isolation structure, in which the gate stack includes a high-k dielectric layer extending from a sidewall of the semiconductor fin to the top surface of the STI structure and terminating prior to reaching the sidewall of the isolation structure, and the high-k dielectric layer is in contact with the top surface of the STI structure. The gate stack includes a gate electrode over the high-k dielectric layer and in contact with the sidewall of the isolation structure.

    SEMICONDUCTOR DEVICE WITH FIN ISOLATION
    78.
    发明申请
    SEMICONDUCTOR DEVICE WITH FIN ISOLATION 有权

    公开(公告)号：US20210013045A1

    公开(公告)日：2021-01-14

    申请号：US17018479

    申请日：2020-09-11

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chang-Yin CHEN ,  Che-Cheng CHANG ,  Chih-Han LIN

    IPC: H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

    Abstract: A first semiconductor fin and a second semiconductor fin are disposed over a substrate. The second semiconductor fin and the first semiconductor fin are aligned substantially along a same line and spaced apart from each other. The first semiconductor fin has a first end portion, the second semiconductor fin has a second end portion, and an end sidewall of the first end portion and is spaced apart from an end sidewall of the second end portion. The gate structure extends substantially perpendicularly to the first semiconductor fin. When viewed from above, the gate structure overlaps with the first end portion of the first semiconductor fin. When viewed from above, the end sidewall of the first end portion of the first semiconductor fin facing the end sidewall of the second end portion of the second semiconductor fin has a re-entrant profile.

    METHOD OF FORMING SEMICONDUCTOR STRUCTURE
    79.
    发明申请
    METHOD OF FORMING SEMICONDUCTOR STRUCTURE 审中-公开

    公开(公告)号：US20200328286A1

    公开(公告)日：2020-10-15

    申请号：US16914940

    申请日：2020-06-29

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chang-Yin CHEN ,  Che-Cheng CHANG ,  Chih-Han LIN

    IPC: H01L29/49 ,  H01L29/66 ,  H01L21/28

    Abstract: A method of forming a semiconductor structure includes forming a dummy gate feature over a semiconductive fin; forming a first spacer around the dummy gate feature and a second spacer around the first spacer; replacing the dummy gate feature with a metal gate feature; after replacing the dummy gate feature with the metal gate feature, partially removing the second spacer such that a top of the second spacer is lower than a top of the first spacer; and depositing a capping layer over and in contact with the metal gate feature and the first spacer.

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