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    Methods and apparatus for extending the effective thermal operating range of a memory
    72.
    发明授权
    Methods and apparatus for extending the effective thermal operating range of a memory 有权
    扩展存储器的有效热操作范围的方法和装置

    公开(公告)号：US08531904B2

    公开(公告)日：2013-09-10

    申请号：US13205820

    申请日：2011-08-09

    Applicant: Tyler J. Thorp ,  Roy E. Scheuerlein

    Inventor： Tyler J. Thorp ,  Roy E. Scheuerlein

    IPC: G11C7/04

    CPC classification number: G11C7/04 ,  G11C16/06

    Abstract: Apparatus and systems are provided for thermal regulation of a memory integrated circuit (“IC”). The apparatus and systems may include a thermal sensor on a memory IC, and a heating element coupled to the thermal sensor. The heating element is adapted to heat the memory IC in response to a signal from the thermal sensor. Other aspects are also provided.

    Abstract translation: 提供了用于存储器集成电路（“IC”）的热调节的装置和系统。 该装置和系统可以包括存储器IC上的热传感器和耦合到热传感器的加热元件。 加热元件适于响应于来自热传感器的信号来加热存储器IC。 还提供其他方面。

    Memory array circuit incorporating multiple array block selection and related method
    73.
    发明授权
    Memory array circuit incorporating multiple array block selection and related method 有权
    包含多个阵列块选择和相关方法的存储阵列电路

    公开(公告)号：US08509025B2

    公开(公告)日：2013-08-13

    申请号：US13215134

    申请日：2011-08-22

    Applicant: Roy E. Scheuerlein ,  Luca G. Fasoli

    Inventor： Roy E. Scheuerlein ,  Luca G. Fasoli

    IPC: G11C8/00

    CPC classification number: G11C8/12 ,  G11C7/1048 ,  G11C7/18 ,  G11C8/08 ,  G11C8/14 ,  Y10T29/49002

    Abstract: Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.

    Abstract translation: 描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。 此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元 并且用于将未选择的偏置条件传送到未选择的阵列块。

    Methods and apparatus for forming memory lines and vias in three dimensional memory arrays using dual damascene process and imprint lithography
    74.
    发明授权
    Methods and apparatus for forming memory lines and vias in three dimensional memory arrays using dual damascene process and imprint lithography 有权
    在使用双镶嵌工艺和压印光刻的三维存储阵列中形成记忆线和通孔的方法和装置

    公开(公告)号：US08466068B2

    公开(公告)日：2013-06-18

    申请号：US11967638

    申请日：2007-12-31

    Applicant: Roy E. Scheuerlein

    Inventor： Roy E. Scheuerlein

    IPC: H01L21/311 ,  H01L21/302

    CPC classification number: H01L21/48 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76817 ,  H01L23/5384 ,  H01L27/10 ,  H01L27/101 ,  H01L2221/1021 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present invention provides systems, apparatus, and methods for forming three dimensional memory arrays using a multi-depth imprint lithography mask and a damascene process. An imprint lithography mask for manufacturing a memory layer in a three dimensional memory is described. The mask includes a translucent material formed with features for making an imprint in a transfer material to be used in a damascene process, the mask having a plurality of imprint depths. At least one imprint depth corresponds to trenches for forming memory lines and at least one depth corresponds to holes for forming vias. Numerous other aspects are disclosed.

    Abstract translation: 本发明提供使用多深度压印光刻掩模和镶嵌工艺形成三维存储器阵列的系统，装置和方法。 描述了用于制造三维存储器中的存储层的压印光刻掩模。 掩模包括半透明材料，其形成有用于在用于镶嵌工艺中的转印材料中进行印记的特征，所述掩模具有多个印痕深度。 至少一个压印深度对应于用于形成存储器线的沟槽，并且至少一个深度对应于用于形成通孔的孔。 公开了许多其他方面。

    Reducing programming time of a memory cell
    75.
    发明授权
    Reducing programming time of a memory cell 有权
    减少存储单元的编程时间

    公开(公告)号：US08441849B2

    公开(公告)日：2013-05-14

    申请号：US13403454

    申请日：2012-02-23

    Applicant: Tyler J. Thorp ,  Roy E. Scheuerlein

    Inventor： Tyler J. Thorp ,  Roy E. Scheuerlein

    IPC: G11C7/06 ,  G11C11/00

    CPC classification number: G11C7/12 ,  G11C7/065 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0061 ,  G11C13/0069

    Abstract: The present invention provides methods and apparatus for adjusting voltages of bit and word lines to program a two terminal memory cell. The invention may include setting a first line connected to a memory cell to a first voltage from a first line standby voltage, charging a second line connected to the memory cell to a predetermined voltage from a second line standby voltage, and switching the first line from the first voltage to a second voltage. The voltage difference between the first voltage and the predetermined voltage is such that a safe voltage results that does not program the memory cell. A voltage difference between the second voltage and the predetermined voltage is such that a programming voltage operative to program the memory cell results.

    Abstract translation: 本发明提供了调节位和字线的电压以编程两个终端存储单元的方法和装置。 本发明可以包括将连接到存储器单元的第一线路从第一线路待机电压设置为第一电压，将连接到存储器单元的第二线路从第二线路待机电压充电到预定电压，以及将第一线路从 第一电压到第二电压。 第一电压和预定电压之间的电压差使得不对存储单元进行编程的安全电压。 第二电压和预定电压之间的电压差使得可操作以编程存储器单元的编程电压结果。

    Capacitive discharge method for writing to non-volatile memory
    77.
    发明授权
    Capacitive discharge method for writing to non-volatile memory 有权
    用于写入非易失性存储器的电容放电方法

    公开(公告)号：US08310892B2

    公开(公告)日：2012-11-13

    申请号：US13237773

    申请日：2011-09-20

    Applicant: Roy E. Scheuerlein ,  Luca G. Fasoli ,  Tianhong Yan

    Inventor： Roy E. Scheuerlein ,  Luca G. Fasoli ,  Tianhong Yan

    IPC: G11C7/00

    CPC classification number: G11C13/0007 ,  G11C7/12 ,  G11C7/22 ,  G11C13/0026 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71

    Abstract: A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The circuits for limiting the SET current provide a charge on one or more bit lines that is not sufficient to SET the memory cells, and then discharge the bit lines through the memory cells in order to SET the memory cells.

    Abstract translation: 存储器系统包括衬底，衬底上的控制电路，包括具有可逆电阻切换元件的多个存储器单元的三维存储器阵列（衬底上方），以及用于限制用于可逆电阻切换的SET电流的电路 元素。 用于限制SET电流的电路在不足以设置存储器单元的一个或多个位线上提供电荷，然后通过存储器单元放电位线以设置存储器单元。

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