Abstract:
A method and apparatus for rapid thermal annealing comprising a plurality of lamps affixed to a lid of the chamber that provide at least one wavelength of light, a laser source extending into the chamber, a substrate support positioned within a base of the chamber, an edge ring affixed to the substrate support, and a gas distribution assembly in communication with the lid and the base of the chamber. A method and apparatus for rapid thermal annealing comprising a plurality of lamps comprising regional control of the lamps and a cooling gas distribution system affixed to a lid of the chamber, a heated substrate support with magnetic levitation extending through a base of the chamber, an edge ring affixed to the substrate support, and a gas distribution assembly in communication with the lid and the base of the chamber.
Abstract:
Methods and apparatus for a solid state non-volatile storage sub-system of a computer is provided. The storage sub-system may include a write-many storage sub-system memory device including write-many memory cells, a write-once storage sub-system memory device including write-once memory cells, and a page-based interface that is adapted to read and write the write-once and write-many storage sub-system memory devices. Numerous other aspects are provided.
Abstract:
Aspects of the invention include a method and apparatus for processing a substrate using a multi-chamber processing system (e.g., a cluster tool) adapted to process substrates in one or more batch and/or single substrate processing chambers to increase the system throughput.
Abstract:
Aspects of the invention include a method and apparatus for processing a substrate using a multi-chamber processing system (e.g., a cluster tool) adapted to process substrates in one or more batch and/or single substrate processing chambers to increase the system throughput. In one embodiment, a system is configured to perform a substrate processing sequence that contains batch processing chambers only, or batch and single substrate processing chambers, to optimize throughput and minimize processing defects due to exposure to a contaminating environment. In one embodiment, a batch processing chamber is used to increase the system throughput by performing a process recipe step that is disproportionately long compared to other process recipe steps in the substrate processing sequence that are performed on the cluster tool. In another embodiment, two or more batch chambers are used to process multiple substrates using one or more of the disproportionately long processing steps in a processing sequence. Aspects of the invention also include an apparatus and method for delivering a precursor to a processing chamber so that a repeatable ALD or CVD deposition process can be performed.
Abstract:
A single wafer cleaning apparatus that includes a rotatable bracket that can hold a wafer, a rinse fluid having a first surface tension, a second fluid having a second surface tension lower than the first surface tension, a first nozzle capable of applying the rinse fluid at a first location on the wafer positioned in the bracket, second nozzle capable of applying the second fluid at a second location on the wafer where the second location is inboard of the first location, and the first nozzle and the second nozzle are capable of moving across the wafer to translate the first location and the second location from the wafer center to the wafer outer edge.
Abstract:
Methods and apparatus for a solid state non-volatile storage sub-system of a computer is provided. The storage sub-system may include a write-once storage sub-system memory device and a write-many storage sub-system memory device. Numerous other aspects are provided.
Abstract:
A method of adjusting the heat transfer properties within a processing chamber is presented. Chamber properties may be determined and adjusted by adjusting the thermal mass of an edge ring disposed in the processing chamber.
Abstract:
Aspects of the invention generally provide an apparatus and method for processing substrates using a multi-chamber processing system that is adapted to process substrates and analyze the results of the processes performed on the substrate. In one aspect of the invention, one or more analysis steps and/or pre-processing steps are performed on the substrate to provide data for processes performed on subsequent substrates. In one aspect of the invention, a system controller and one or more analysis devices are utilized to monitor and control a process chamber recipe and/or a process sequence to reduce substrate scrap due to defects in the formed device and device performance variability issues. Embodiments of the present invention also generally provide methods and a system for repeatably and reliably forming semiconductor devices used in a variety of applications.
Abstract:
A polysilicon film is formed with enhanced selectivity by flowing chlorine during the formation of the film. The chlorine acts as an etchant to insulative areas adjacent polysilicon structures on which the film is desired to be formed. Bottom electrodes for capacitors are formed using this process, followed by an anneal to create hemishperical grain (HSG) polysilicon. Multilayer capacitor containers are formed in a non-oxidizing ambient so that no oxide is formed between the layers. The structure formed is planarized to form separate containers made from doped and undoped amorphous silicon layers. Selected ones of undoped layers are seeded in a chlorine containing environment and annealed to form HSG. A dielectric layer and second electrode are formed to complete the cell capacitor.
Abstract:
Disclosed is an electrical device having, and a process for forming, a shallow junction with a variable concentration profile gradation of dopants. The process of the present invention includes first providing and masking a surface on an in-process integrated circuit wafer on which the shallow junction is to be formed. Next, a low ion velocity and low energy ion bombardment plasma doping or PLAD operation is conducted to provide a highly doped inner portion of a shallow junction. In a further step, a higher ion velocity and energy conventional ion bombardment implantation doping operation is conducted using a medium power implanter to extend the shallow junction boundaries with a lightly doped outer portion. In various embodiments, the doping steps can be performed in reverse order. In addition, an anneal step can be performed after any doping operation.