公开(公告)号：US08236610B2

公开(公告)日：2012-08-07

申请号：US12471656

申请日：2009-05-26

Applicant: Louis Lu-Chen Hsu ,  Kangguo Cheng ,  Timothy J. Dalton ,  Mukta G. Farooq ,  John A. Fitzsimmons

Inventor： Louis Lu-Chen Hsu ,  Kangguo Cheng ,  Timothy J. Dalton ,  Mukta G. Farooq ,  John A. Fitzsimmons

IPC: H01L21/00 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/14 ,  H01L21/6836 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L27/0207 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/06183 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/14183 ,  H01L2224/16 ,  H01L2224/16105 ,  H01L2224/16137 ,  H01L2224/16147 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Systems and methods are disclosed that enable forming semiconductor chip connections. In one embodiment, the semiconductor chip includes a body having a polyhedron shape with a pair of opposing sides; and a solder member extending along a side that extends between the pair of opposing sides of the polyhedron shape.

Abstract translation: 公开了能够形成半导体芯片连接的系统和方法。 在一个实施例中，半导体芯片包括具有一对相对侧面的多面体形状的主体; 以及沿着在多面体形状的一对相对侧之间延伸的一侧延伸的焊料构件。

公开(公告)号：US20120193713A1

公开(公告)日：2012-08-02

申请号：US13017966

申请日：2011-01-31

Applicant: Pranita Kulkarni ,  Ali Khakifirooz ,  Kangguo Cheng ,  Bruce B. Doris ,  Ghavam Shahidi ,  Hemanth Jagannathan

Inventor： Pranita Kulkarni ,  Ali Khakifirooz ,  Kangguo Cheng ,  Bruce B. Doris ,  Ghavam Shahidi ,  Hemanth Jagannathan

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/66803 ,  H01L29/41791 ,  H01L29/785

Abstract: A fin field-effect transistor (finFET) device having reduced capacitance, access resistance, and contact resistance is formed. A buried oxide, a fin, a gate, and first spacers are provided. The fin is doped to form extension junctions extending under the gate. Second spacers are formed on top of the extension junctions. Each is second spacer adjacent to one of the first spacers to either side of the gate. The extension junctions and the buried oxide not protected by the gate, the first spacers, and the second spacers are etched back to create voids. The voids are filled with a semiconductor material such that a top surface of the semiconductor material extending below top surfaces of the extension junctions, to form recessed source-drain regions. A silicide layer is formed on the recessed source-drain regions, the extension junctions, and the gate not protected by the first spacers and the second spacers.

Abstract translation: 形成具有减小的电容，存取电阻和接触电阻的鳍状场效应晶体管（finFET）器件。 提供掩埋氧化物，鳍状物，栅极和第一间隔物。 该鳍被掺杂以形成在栅极下方延伸的延伸结。 第二间隔件形成在延伸接头的顶部。 每个是与栅极的任一侧相邻的第一间隔件之间的第二间隔件。 延伸结和未被栅极保护的埋入氧化物，第一间隔物和第二间隔物被回蚀刻以产生空隙。 空隙填充有半导体材料，使得半导体材料的顶表面延伸到延伸接头的顶表面之下，以形成凹陷的源极 - 漏极区域。 在凹陷的源极 - 漏极区域，延伸结点和不被第一间隔物和第二间隔物保护的栅极上形成硅化物层。

公开(公告)号：US20120187465A1

公开(公告)日：2012-07-26

申请号：US13434883

申请日：2012-03-30

Applicant: Kangguo Cheng ,  Byeong Y. Kim ,  Munir D. Naeem ,  James P. Norum

Inventor： Kangguo Cheng ,  Byeong Y. Kim ,  Munir D. Naeem ,  James P. Norum

IPC: H01L29/94

CPC classification number: H01L21/84 ,  H01L27/1087 ,  H01L28/84 ,  H01L29/66181 ,  H01L29/945

Abstract: An integrated circuit including a trench capacitor has a semiconductor region in which a material composition varies in a quantity of at least one component therein such that the quantity alternates with depth a plurality of times between at least two different values. For example, a concentration of a dopant or a weight percentage of a second semiconductor material, such as germanium, in a semiconductor alloy can alternate between with depth a plurality of times between higher and lower values. The trench capacitor has an undulating capacitor dielectric layer, wherein the undulations of the capacitor dielectric layer are at least partly determined by the undulating interior surface of the trench. Such trench capacitor can provide enhanced capacitance, and can be incorporated in a memory cell such as a dynamic random access memory (“DRAM”) cell, for example.

Abstract translation: 包括沟槽电容器的集成电路具有半导体区域，其中材料组成在其中至少一个分量的量变化，使得该量在至少两个不同值之间多次交替深度。 例如，半导体合金中的掺杂剂的浓度或第二半导体材料（例如锗）的重量百分比可以在较高和较低值之间的深度之间交替多次。 沟槽电容器具有波动的电容器介电层，其中电容器介电层的起伏至少部分地由沟槽的起伏内表面确定。 这种沟槽电容器可以提供增强的电容，并且可以并入诸如动态随机存取存储器（“DRAM”）的存储单元中。

公开(公告)号：US20120184073A1

公开(公告)日：2012-07-19

申请号：US13433423

申请日：2012-03-29

Applicant: Roger A. Booth, JR. ,  Kangguo Cheng ,  Chandrasekharan Kothandaraman ,  Chengwen Pei

Inventor： Roger A. Booth, JR. ,  Kangguo Cheng ,  Chandrasekharan Kothandaraman ,  Chengwen Pei

IPC: H01L21/336

CPC classification number: H01L29/78 ,  H01L21/28282 ,  H01L21/823462 ,  H01L21/823468 ,  H01L27/1052 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/792

Abstract: A method of fabricating a memory device is provided that may begin with forming a layered gate stack atop a semiconductor substrate and patterning a metal electrode layer stopping on the high-k gate dielectric layer of the layered gate stack to provide a first metal gate electrode and a second metal gate electrode on the semiconductor substrate. In a next process sequence, at least one spacer is formed on the first metal gate electrode atop a portion of the high-k gate dielectric layer, wherein a remaining portion of the high-k gate dielectric is exposed. The remaining portion of the high-k gate dielectric layer is etched to provide a first high-k gate dielectric having a portion that extends beyond a sidewall of the first metal gate electrode and a second high-k gate dielectric having an edge that is aligned to a sidewall of the second metal gate electrode.

Abstract translation: 提供一种制造存储器件的方法，其可以开始于在半导体衬底顶上形成分层栅极堆叠并且图案化停止在层状栅叠层的高k栅极电介质层上的金属电极层，以提供第一金属栅电极和 半导体衬底上的第二金属栅电极。 在下一个处理顺序中，在第一金属栅电极的高k栅介质层的一部分顶上形成至少一个间隔物，其中高k栅极电介质的剩余部分被暴露。 蚀刻高k栅极电介质层的剩余部分以提供具有延伸超过第一金属栅电极的侧壁的部分的第一高k栅极电介质和具有对准边缘的第二高k栅极电介质 到第二金属栅电极的侧壁。

公开(公告)号：US08207038B2

公开(公告)日：2012-06-26

申请号：US12786397

申请日：2010-05-24

Applicant: Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC: H01L21/336

CPC classification number: H01L29/7843 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: A method for fabricating an FET device is disclosed. The method includes Fin-FET devices with fins that are composed of a first material, and then merged together by epitaxial deposition of a second material. The fins are vertically recesses using a selective etch. A continuous silicide layer is formed over the increased surface areas of the first material and the second material, leading to smaller resistance. A stress liner overlaying the FET device is afterwards deposited. An FET device is also disclosed, which FET device includes a plurality of Fin-FET devices, the fins of which are composed of a first material. The FET device includes a second material, which is epitaxially merging the fins. The fins are vertically recessed relative to an upper surface of the second material. The FET device furthermore includes a continuous silicide layer formed over the fins and over the second material, and a stress liner covering the device.

Abstract translation: 公开了一种用于制造FET器件的方法。 该方法包括具有由第一材料构成的翅片的Fin-FET器件，然后通过外延沉积第二材料而合并在一起。 翅片是使用选择性蚀刻的垂直凹部。 在第一材料和第二材料的增加的表面积上形成连续的硅化物层，导致较小的电阻。 覆盖FET器件的应力衬垫之后被沉积。 还公开了一种FET器件，该FET器件包括多个Fin-FET器件，其翅片由第一材料构成。 FET器件包括第二材料，其外延地融合鳍片。 翅片相对于第二材料的上表面垂直凹入。 FET器件还包括形成在鳍片上方和第二材料上的连续硅化物层，以及覆盖该器件的应力衬垫。

公开(公告)号：US20120146112A1

公开(公告)日：2012-06-14

申请号：US13396291

申请日：2012-02-14

Applicant: Kangguo Cheng ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  John Edward Sheets, II

Inventor： Kangguo Cheng ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  John Edward Sheets, II

IPC: H01L29/772

CPC classification number: H01L29/785 ,  H01L29/045 ,  H01L29/66818

Abstract: Embodiments of the invention provide a relatively uniform width fin in a Fin Field Effect Transistors (FinFETs) and apparatus and methods for forming the same. A fin structure may be formed such that the surface of a sidewall portion of the fin structure is normal to a first crystallographic direction. Tapered regions at the end of the fin structure may be normal to a second crystal direction. A crystallographic dependent etch may be performed on the fin structure. The crystallographic dependent etch may remove material from portions of the fin normal to the second crystal direction relatively faster, thereby resulting in a relatively uniform width fin structure.

Abstract translation: 本发明的实施例提供了Fin场效应晶体管（FinFET）中的相对均匀的宽度鳍片及其形成方法。 翅片结构可以形成为使翅片结构的侧壁部分的表面垂直于第一结晶方向。 翅片结构端部的锥形区域可以垂直于第二晶体方向。 可以对翅片结构进行晶体依赖蚀刻。 晶体依赖蚀刻可以相对较快地从第二晶体方向垂直于翅片的部分去除材料，从而形成相对均匀的宽度鳍片结构。

公开(公告)号：US20120080802A1

公开(公告)日：2012-04-05

申请号：US12894218

申请日：2010-09-30

Applicant: Kangguo Cheng ,  Subramanian Iyer ,  Ali Khakifirooz ,  Pranita Kulkarni

Inventor： Kangguo Cheng ,  Subramanian Iyer ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L21/486 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/268 ,  H01L21/324 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5384 ,  H01L29/36 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes an epitaxy layer formed on semiconductor substrate, a device layer formed on the epitaxy layer, a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor, and a deep trench isolation structure formed within the substrate and surrounding the through-silicon via conductor. A region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device, thereby decreasing parasitic capacitance.

Abstract translation: 半导体器件包括形成在半导体衬底上的外延层，形成在外延层上的器件层，在半导体衬底内形成的沟槽，并且包括在沟槽内形成衬垫的介电层和形成穿硅通孔导体的导电芯 ，以及形成在衬底内并围绕通过硅通孔导体的深沟槽隔离结构。 形成在贯通硅通孔导体和深沟槽隔离结构之间的外延层的区域与施加到半导体器件的任何信号电隔离，从而降低寄生电容。

公开(公告)号：US20120064694A1

公开(公告)日：2012-03-15

申请号：US12880419

申请日：2010-09-13

Applicant: Roger A. BOOTH, JR. ,  Kangguo CHENG ,  Joseph ERVIN ,  Chengwen PEI ,  Ravi M. TODI ,  Geng WANG ,  Yanli ZHANG

Inventor： Roger A. BOOTH, JR. ,  Kangguo CHENG ,  Joseph ERVIN ,  Chengwen PEI ,  Ravi M. TODI ,  Geng WANG ,  Yanli ZHANG

IPC: H01L21/02

CPC classification number: H01L29/66181 ,  H01L27/1087

Abstract: A method of forming a deep trench structure for a semiconductor device includes forming a mask layer over a semiconductor substrate. An opening in the mask layer is formed by patterning the mask layer, and a deep trench is formed in the semiconductor substrate using the patterned opening in the mask layer. A sacrificial fill material is formed over the mask layer and into the deep trench. A first portion of the sacrificial fill material is recessed from the deep trench and a first dopant implant forms a first doped region in the semiconductor substrate. A second portion of the sacrificial fill material is recessed from the deep trench and a second dopant implant forms a second doped region in the semiconductor substrate, wherein the second doped region is formed underneath the first doped region such that the second doped region and the first doped region are contiguous with each other.

Abstract translation: 形成半导体器件的深沟槽结构的方法包括在半导体衬底上形成掩模层。 通过对掩模层进行构图来形成掩模层中的开口，并且使用掩模层中的图案化开口在半导体衬底中形成深沟槽。 牺牲填充材料形成在掩模层上并进入深沟槽中。 牺牲填充材料的第一部分从深沟槽凹陷，并且第一掺杂剂注入在半导体衬底中形成第一掺杂区域。 牺牲填充材料的第二部分从深沟槽凹陷，并且第二掺杂剂注入在半导体衬底中形成第二掺杂区，其中第二掺杂区形成在第一掺杂区的下方，使得第二掺杂区和第一掺杂区 掺杂区域彼此邻接。

公开(公告)号：US20120061762A1

公开(公告)日：2012-03-15

申请号：US12881152

申请日：2010-09-13

Applicant: Kangguo Cheng ,  Bruce B. Doris ,  Ying Zhang

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ying Zhang

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/66795 ,  H01L21/2633 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/517 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/7856

Abstract: Asymmetric FET devices, and a method for fabricating such asymmetric devices on a fin structure is disclosed. The fabrication method includes disposing over the fin a high-k dielectric layer followed by a threshold-modifying layer, performing an ion bombardment at a tilted angle which removes the threshold-modifying layer over one of the fin's side-surfaces. The completed FET devices will be asymmetric due to the threshold-modifying layer being present only in one of two devices on the side of the fin. In an alternate embodiment further asymmetries are introduced, again using tilted ion implantation, resulting in differing gate-conductor materials for the two FinFET devices on each side of the fin.

公开(公告)号：US20110316083A1

公开(公告)日：2011-12-29

申请号：US12823798

申请日：2010-06-25

Applicant: Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Pranita Kulkarni

Inventor： Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66545 ,  H01L29/78648

Abstract: A back-gated field effect transistor (FET) includes a substrate, the substrate comprising top semiconductor layer on top of a buried dielectric layer on top of a bottom semiconductor layer; a front gate located on the top semiconductor layer; a channel region located in the top semiconductor layer under the front gate; a source region located in the top semiconductor layer on a side of the channel region, and a drain region located in the top semiconductor layer on the side of the channel region opposite the source regions; and a back gate located in the bottom semiconductor layer, the back gate configured such that the back gate abuts the buried dielectric layer underneath the channel region, and is separated from the buried dielectric layer by a separation distance underneath the source region and the drain region.

Abstract translation: 背栅式场效应晶体管（FET）包括衬底，该衬底包括位于底部半导体层顶部的掩埋电介质层顶部的顶部半导体层; 位于顶部半导体层上的前门; 位于前门下的顶部半导体层中的沟道区; 位于沟道区一侧的顶部半导体层中的源极区域和位于与源极区域相反的沟道区域侧的顶部半导体层中的漏极区域; 以及位于底部半导体层中的背栅，后栅配置成使得后栅极邻接沟道区下方的掩埋介电层，并且在源极区和漏极区之下与掩埋介电层分离距离 。