公开(公告)号：US20230268316A1

公开(公告)日：2023-08-24

申请号：US17674847

申请日：2022-02-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sung-Yueh Wu ,  Chien-Ling Hwang ,  Jen-Chun Liao ,  Ching-Hua Hsieh

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L24/96 ,  H01L24/16 ,  H01L23/49822 ,  H01L23/3114 ,  H01L21/561 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/81947

摘要： A package structure includes a semiconductor device including a conductive feature, a joint layer, a pillar structure, an encapsulant and a RDL structure. The joint layer is disposed on the conductive feature. The pillar structure is disposed on and coupled to the semiconductor device through the joint layer. The encapsulant laterally encapsulates the semiconductor device and the pillar structure. The RDL structure is electrically connected to the semiconductor device.

公开(公告)号：US20230253395A1

公开(公告)日：2023-08-10

申请号：US18302063

申请日：2023-04-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsien-Wei Chen ,  Jie Chen

IPC分类号： H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

CPC分类号： H01L25/50 ,  H01L24/02 ,  H01L24/09 ,  H01L23/3107 ,  H01L24/73 ,  H01L24/81 ,  H01L21/568 ,  H01L23/49811 ,  H01L21/4853 ,  H01L24/03 ,  H01L21/6835 ,  H01L24/92 ,  H01L24/96 ,  H01L21/6836 ,  H01L25/0657 ,  H01L25/10 ,  H01L25/18 ,  H01L25/065 ,  H01L25/105 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/565 ,  H01L24/48 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/0905 ,  H01L2224/48137 ,  H01L2224/13008 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2224/45144 ,  H01L23/3114 ,  H01L23/3128 ,  H01L21/561 ,  H01L2224/0401 ,  H01L2224/48091 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/13084 ,  H01L2224/81895 ,  H01L2224/13311 ,  H01L2224/13181 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/03003 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/13021 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48227 ,  H01L2224/81005 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/92 ,  H01L2224/96 ,  H01L2224/13166 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/45147 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/3511 ,  H01L2224/2518 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2224/451 ,  H01L21/304

摘要： Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side.

公开(公告)号：US20230230849A1

公开(公告)日：2023-07-20

申请号：US17661940

申请日：2022-05-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Shen Cheng ,  Chia-Lun Chang ,  Hao-Jan Pei ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh

IPC分类号： H01L21/48 ,  H01L25/10 ,  B23K26/362

CPC分类号： H01L21/481 ,  B23K26/362 ,  H01L21/4853 ,  H01L25/105 ,  H01L24/96

摘要： A method includes forming an insulating layer over a package. The package has a plurality of locations where openings are subsequently formed. A first laser shot is performed, location by location, on each of the locations across the package. A first laser spot of the first laser shot overlaps with each of the locations. The first laser shot removes a first portion of the insulating layer below the first laser spot. Another laser shot is performed, location by location, on each of the locations across the package. Another laser spot of the another laser shot overlaps with each of the locations. The another laser shot removes another portion of the insulating layer below the another laser spot. Performing the another laser shot, location by location, on each of the locations across the package is repeated multiple times, until desired portions of the insulating layer are removed.

公开(公告)号：US20230223348A1

公开(公告)日：2023-07-13

申请号：US18163033

申请日：2023-02-01

申请人： Apple Inc.

发明人： Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu

IPC分类号： H01L23/538 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065 ,  H01L21/683 ,  H01L25/10 ,  H01L23/16 ,  H01L23/498 ,  H01L23/31 ,  H01L25/18

CPC分类号： H01L23/5385 ,  H01L25/50 ,  H01L21/486 ,  H01L24/96 ,  H01L25/0655 ,  H01L23/5383 ,  H01L24/19 ,  H01L23/5386 ,  H01L21/4853 ,  H01L21/6835 ,  H01L25/105 ,  H01L23/16 ,  H01L23/5384 ,  H01L23/49833 ,  H01L2924/15192 ,  H01L2224/92125 ,  H01L24/16 ,  H01L23/49827 ,  H01L2225/1023 ,  H01L2924/19105 ,  H01L2924/19011 ,  H01L2224/131 ,  H01L2224/12105 ,  H01L23/3128 ,  H01L2924/37001 ,  H01L2224/81005 ,  H01L2225/1094 ,  H01L2924/3511 ,  H01L2224/92225 ,  H01L2224/16237 ,  H01L23/49822 ,  H01L2924/1432 ,  H01L2224/04105 ,  H01L2924/15311 ,  H01L2924/1431 ,  H01L2224/16227 ,  H01L2221/68359 ,  H01L2924/19043 ,  H01L24/73 ,  H01L23/49816 ,  H01L2224/1703 ,  H01L2924/1434 ,  H01L24/17 ,  H01L21/4857 ,  H01L2224/16235 ,  H01L2224/0401 ,  H01L2924/19042 ,  H01L2924/19041 ,  H01L2224/73267 ,  H01L2225/1058 ,  H01L2224/73253 ,  H01L24/13 ,  H01L25/18 ,  H01L2224/97 ,  H01L2224/92244 ,  H01L2224/32225 ,  H01L24/32 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/73204

摘要： Multiple component package structures are described in which an interposer chiplet is integrated to provide fine routing between components. In an embodiment, the interposer chiplet and a plurality of conductive vias are encapsulated in an encapsulation layer. A first plurality of terminals of the first and second components may be in electrical connection with the plurality of conductive pillars and a second plurality of terminals of first and second components may be in electrical connection with the interposer chiplet.

公开(公告)号：US20230212061A1

公开(公告)日：2023-07-06

申请号：US17927190

申请日：2021-05-18

申请人： Nippon Electric Glass Co., Ltd.

发明人： Ryota SUZUKI ,  Ken YUKI ,  Tetsuya MURATA ,  Tomonori ICHIMARU ,  Yuta NAGANO

IPC分类号： C03C3/11 ,  C03C3/097 ,  C03C3/095 ,  C03C3/083 ,  C03C3/085 ,  C03C3/087 ,  C03C3/093 ,  H01L23/00 ,  H01L21/687

CPC分类号： C03C3/11 ,  C03C3/097 ,  C03C3/095 ,  C03C3/083 ,  C03C3/085 ,  C03C3/087 ,  C03C3/093 ,  H01L24/96 ,  H01L21/68757 ,  H01L2224/96

摘要： A support glass substrate of the present invention is a support glass substrate for supporting a substrate to be processed, the support glass substrate including lithium aluminosilicate-based glass, having a content of Li2O of from 0.02 mol % to 25 mol % in a glass composition, and having an average linear thermal expansion coefficient within a temperature range of from 30° C. to 380° C. of 38×10−7/° C. or more and 160×10−7/° C. or less.

公开(公告)号：US20230197690A1

公开(公告)日：2023-06-22

申请号：US18175284

申请日：2023-02-27

申请人： Micron Technology, Inc.

发明人： Tongbi Jiang ,  Yong Poo Chia

IPC分类号： H01L25/07 ,  H01L25/00 ,  H01L23/31 ,  H01L23/48 ,  H01L21/768 ,  H01L21/82 ,  H01L23/00 ,  H01L21/56 ,  H01L23/538 ,  H01L25/10

CPC分类号： H01L25/071 ,  H01L21/82 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L25/105 ,  H01L2221/68359 ,  H01L2224/20 ,  H01L2224/838 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/83193 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/06548 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19043

摘要： A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material.

公开(公告)号：US20230187362A1

公开(公告)日：2023-06-15

申请号：US17548078

申请日：2021-12-10

申请人： Intel Corporation

发明人： Adel A. Elsherbini ,  Christopher M. Pelto ,  Kimin Jun ,  Brandon M. Rawlings ,  Shawna M. Liff ,  Bradley A. Jackson ,  Robert J. Munoz ,  Johanna M. Swan

IPC分类号： H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00 ,  H01L23/00

CPC分类号： H01L23/5383 ,  H01L25/0652 ,  H01L23/49894 ,  H01L25/50 ,  H01L24/96

摘要： A microelectronic assembly is provided, comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer; and a third plurality of IC dies in a third layer, in which: the second layer is between the first layer and the third layer, an interface between two adjacent layers comprises interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects, and each of the first layer, the second layer, and the third layer comprises a dielectric material, and further comprises conductive traces in the dielectric material.

公开(公告)号：US20230163092A1

公开(公告)日：2023-05-25

申请号：US17868308

申请日：2022-07-19

申请人： Samsung Electronics Co., Ltd.

发明人： Soohwan Lee

IPC分类号： H01L23/00 ,  H01L25/065

CPC分类号： H01L24/32 ,  H01L25/0657 ,  H01L24/16 ,  H01L24/73 ,  H01L2924/35121 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L24/81 ,  H01L2224/81203 ,  H01L24/96 ,  H01L24/97 ,  H01L2924/15311 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/18301 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32059 ,  H01L2224/26175 ,  H01L2224/32054

摘要： A semiconductor package includes a semiconductor chip on a package substrate, a dam structure disposed on the package substrate and surrounding the semiconductor chip, the dam structure including a first dam portion having a first length in a vertical direction, and a second dam portion connected to the first dam portion and extending from an outer side of the first dam portion, and having a second length less than the first length in the vertical direction, and an adhesive layer disposed on the package substrate, the adhesive layer including a first adhesive portion disposed between the semiconductor chip and the package substrate and overlapping the semiconductor chip in the vertical direction, and a second adhesive portion on an outer side of the semiconductor chip and including at least a part contacting a top surface of the first dam portion.

公开(公告)号：US20230154876A1

公开(公告)日：2023-05-18

申请号：US18093880

申请日：2023-01-06

申请人： Samsung Electronics Co., Ltd.

发明人： Minjung CHOI ,  Sooho SHIN ,  Yeonjin LEE ,  Junghoon HAN

IPC分类号： H01L23/00 ,  H01L21/56

CPC分类号： H01L24/05 ,  H01L21/561 ,  H01L24/13 ,  H01L24/96 ,  H01L24/73 ,  H01L2224/81801 ,  H01L2924/1304 ,  H01L2924/18162 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/12105

摘要： A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.

公开(公告)号：US11652085B2

公开(公告)日：2023-05-16

申请号：US17830290

申请日：2022-06-01

申请人： SJ Semiconductor(Jiangyin) Corporation

发明人： Hailin Zhao

IPC分类号： H01L23/00 ,  H01L21/56

CPC分类号： H01L24/96 ,  H01L21/561 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/95001

摘要： The present disclosure provides a fan-out wafer-level packaging structure and a method for packaging the same. The structure includes: two or more semiconductor chips with a bonding pad, the semiconductor chips are arranged in a fan-out wafer array, and each of the semiconductor chips has an initial position, respectively; a plastic packaging layer, covering surfaces of the semiconductor chips and between the semiconductor chips, each of the semiconductor chips has an offset position, respectively, and the offset position has an offset distance relative to the initial position; a redistribution layer formed on the semiconductor chips, to realize interconnection between the semiconductor chips, the redistribution layer includes at least one first redistribution layer, the first redistribution layer is formed on a surface of the semiconductor chips and is aligned and in contact with the bonding pad of the semiconductor chips; and a metal bump formed on the redistribution layer.