公开(公告)号：US20240088033A1

公开(公告)日：2024-03-14

申请号：US18186206

申请日：2023-03-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chao-Kai Chan ,  Chung-Hao Tsai ,  Chuei-Tang WANG ,  Wei-Ting Chen

IPC: H01L23/528 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/06 ,  H01L29/423 ,  H01L29/94

CPC classification number: H01L23/5283 ,  H01L21/823412 ,  H01L21/823475 ,  H01L23/5226 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/945

Abstract: A method of forming a semiconductor device is provided. A transistor is formed at a first side of the substrate and a first dielectric layer is formed aside the transistor. A first metal via is formed through the first dielectric layer and aside the transistor. A first interconnect structure is formed over the first side of the substrate and electrically connected to the transistor and the first metal via. The substrate is thinned from a second side of the substrate. A capacitor is formed at the second side of the substrate and a second dielectric layer is formed aside the capacitor. A second metal via is formed through the second dielectric layer and the substrate and electrically connected to the first metal via.

公开(公告)号：US20240088030A1

公开(公告)日：2024-03-14

申请号：US18158137

申请日：2023-01-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chin-Liang CHEN ,  Chi-Yu LU ,  Ching-Wei TSAI ,  Chun-Yuan CHEN ,  Li-Chun TIEN

IPC: H01L23/528 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/12

CPC classification number: H01L23/528 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/5226 ,  H01L27/12

Abstract: Provided are semiconductor devices that include a first gate structure having a first end cap portion, a second gate structure having a second end cap portion coaxial with the first gate structure, a first dielectric region separating the first end cap portion and the second end cap portion, a first conductive element extending over the first gate structure, a second conductive element extending over the second gate structure, and a gate via electrically connecting the second gate structure and the second conductive element, with the first dielectric region having a first width and being positioned at least partially under the first conductive element and defines a spacing between the gate via and an end of the second end cap portion that exceeds a predetermined distance.

公开(公告)号：US20240079329A1

公开(公告)日：2024-03-07

申请号：US18162920

申请日：2023-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： EUN SUNG KIM ,  JAE YOUNG CHOI ,  WONHYUK HONG ,  SEUNGCHAN YUN ,  JAEJIK BAEK ,  SEUNG MIN SONG ,  KANG-ILL SEO

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/535

CPC classification number: H01L23/5286 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/535

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include forming a sacrificial layer in a preliminary substrate by adding an element into the preliminary substrate, forming a transistor structure on the preliminary substrate, the transistor structure including a source/drain region, replacing the sacrificial layer with a power contact that comprises an upper surface contacting the source/drain region, and forming a power rail that contacts a lower surface of the power contact.

公开(公告)号：US20240072117A1

公开(公告)日：2024-02-29

申请号：US18307259

申请日：2023-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gukhee Kim ,  Kyoungwoo Lee ,  Jeewoong Kim ,  Sangcheol Na ,  Minchan Gwak ,  Youngwoo Kim ,  Anthony Dongick Lee

IPC: H01L29/08 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/0847 ,  H01L21/823475 ,  H01L27/088

Abstract: A semiconductor device includes a substrate having a first and second active patterns therein, first and second source/drain patterns extending on the first and second active patterns, respectively, and an active contact on the first and second source/drain patterns. An upper contact is provided, which extends from the active contact towards the substrate, and between the first and second active patterns. A lower power interconnection line is provided, which is buried in a lower portion of the substrate and includes: a buried interconnection portion having a line shape, and a lower contact portion extending vertically from the buried interconnection portion to a bottom surface of the upper contact. A barrier pattern is provided, which extends between the lower contact portion and the upper contact, but not between the buried interconnection portion and the lower contact portion.

公开(公告)号：US20240071925A1

公开(公告)日：2024-02-29

申请号：US17898765

申请日：2022-08-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Liqiao Qin ,  Tao Li ,  Ruilong Xie ,  Chen Zhang ,  Kisik Choi

IPC: H01L23/528 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/088 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L23/5286 ,  H01L21/823418 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/088 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/66545 ,  H01L29/42392

Abstract: Semiconductor devices and methods of forming the same include a semiconductor base having a first width. A semiconductor device over the semiconductor base has a second width that is greater than the first width. A power rail is beneath the semiconductor base. A conductive contact extends from a top of the semiconductor device to the power rail.

公开(公告)号：US20240063211A1

公开(公告)日：2024-02-22

申请号：US18447999

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wei-Ling Chang ,  Jung-Chan Yang ,  Li-Chun Tien ,  Ting Yu Chen

IPC: H01L27/02 ,  H01L21/8234 ,  H01L27/088 ,  H03K19/17772

CPC classification number: H01L27/0207 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H03K19/17772

Abstract: A power gating cell on an integrated circuit is provided. The power gating cell includes: a central area; a peripheral area surrounding the central area; a first active region located in the central area, the first active region having a first width in a first direction corresponding to at least four fin structures extending in a second direction perpendicular to the first direction; and a plurality of second active regions located in the peripheral area, each second active region having a second width in the first direction corresponding to at least one and no more than three fin structures extending in the second direction.

公开(公告)号：US20240063126A1

公开(公告)日：2024-02-22

申请号：US17889894

申请日：2022-08-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Lin-Chen Lu ,  Tsung-Han Tsai

IPC: H01L23/532 ,  H01L23/66 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L23/53295 ,  H01L23/66 ,  H01L21/7682 ,  H01L21/76828 ,  H01L21/76832 ,  H01L23/5283 ,  H01L23/5222 ,  H01L27/088 ,  H01L21/823475 ,  H01L2223/6616 ,  H01L2223/6644 ,  H01L21/76826

Abstract: A semiconductor device structure and methods of forming the same are described. In some embodiments, the structure includes a device and a first dielectric layer disposed over the device. An airgap is located in the first dielectric layer. The structure further includes a conductive feature disposed in the first dielectric layer, and the first dielectric layer includes a first portion disposed between the airgap and a first side of the conductive feature and a second portion disposed adjacent a second side of the conductive feature opposite the first side. The first portion has a first nitrogen concentration, and the second portion has a second nitrogen concentration substantially less than the first nitrogen concentration.

公开(公告)号：US20240063115A1

公开(公告)日：2024-02-22

申请号：US17891421

申请日：2022-08-19

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-ZHONG LI ,  HSIH-YANG CHIU

IPC: H01L23/525 ,  H01L23/528 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L23/5256 ,  H01L23/5283 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/42356 ,  H01L27/088 ,  H01L21/823425 ,  H01L21/823475 ,  H01L21/823481

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate; a transistor disposed over the substrate; and a trench fuse disposed in the substrate and penetrating a source/drain (S/D) region of the transistor. A method for manufacturing the semiconductor structure is also provided.

公开(公告)号：US11908906B2

公开(公告)日：2024-02-20

申请号：US17446017

申请日：2021-08-26

Applicant: Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

Inventor： Hailong Yu ,  Xuezhen Jing ,  Hao Zhang ,  Tiantian Zhang ,  Jinhui Meng

IPC: H01L29/417 ,  H01L27/088 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L29/41725 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0649

Abstract: A semiconductor structure and a fabrication method of the semiconductor structure are provided. The method includes providing a substrate, forming a first dielectric layer and a plurality of gate structures, forming source-drain doped regions, and forming a source-drain plug. The first dielectric layer covers surfaces of the gate structure, the source-drain doped region and the source-drain plug. The method also includes forming a first plug in the first dielectric layer, and forming a second dielectric layer on the first dielectric layer. The first plug is in contact with a top surface of one of the source-drain plug and the gate structure. The second dielectric layer covers the first plug. Further, the method includes forming a second plug material film in the first and second dielectric layers. The second plug material film is in contact with the top surface of one of the source-drain plug and the gate structure.

公开(公告)号：US11901219B2

公开(公告)日：2024-02-13

申请号：US17406920

申请日：2021-08-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yi-Wen Pan ,  You-Lan Li ,  Chung-Chi Ko

IPC: H01L21/768 ,  H01L21/8234 ,  H01L21/762

CPC classification number: H01L21/76814 ,  H01L21/76224 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823475

Abstract: Methods of forming a semiconductor device structure are described. In some embodiments, the method includes forming an interconnect structure over a substrate. The forming the interconnect structure over the semiconductor device structure includes forming a dielectric layer, then performing an annealing process, then forming one or more openings in the dielectric layer, then performing a first ultraviolet (UV) curing process, and then forming conductive features in the one or more openings.