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    FIN FIELD EFFECT TRANSISTORS HAVING HETEROEPITAXIAL CHANNELS
    61.
    发明申请
    FIN FIELD EFFECT TRANSISTORS HAVING HETEROEPITAXIAL CHANNELS 有权
    具有异常通道的FIN场效应晶体管

    公开(公告)号：US20150206876A1

    公开(公告)日：2015-07-23

    申请号：US14158987

    申请日：2014-01-20

    Applicant: International Business Machines Corporation

    Inventor： Emre Alptekin ,  Wing L. Lai ,  Ravikumar Ramachandran ,  Matthew W. Stoker ,  Henry K. Utomo ,  Reinaldo A. Vega

    IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/306 ,  H01L21/8234

    CPC classification number: H01L27/0886 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/6681

    Abstract: Disposable gate structures are formed over semiconductor material portions, and source and drain regions can be formed in the semiconductor material portions. After formation of a planarization dielectric layer, one type of disposable gate structure can be removed selective to at least another type of disposable gate structure employing a patterned hard dielectric mask layer. After recessing a surface portion of a body portion, a heteroepitaxial channel portion is formed on the remaining physically exposed portion of the body portion by selective epitaxy of a semiconductor material different from the semiconductor material of the remaining body portion. A plurality of types of heteroepitaxial channel portions can be formed in different types of semiconductor devices. Replacement gate structures can be formed in the gate cavities to provide field effect transistors having different threshold voltages.

    Abstract translation: 在半导体材料部分上形成一次性栅极结构，并且可以在半导体材料部分中形成源极和漏极区域。 在形成平坦化介电层之后，可以选择性地去除一种类型的一次性栅极结构至少使用图案化的硬介电掩模层的另一种类型的一次性栅极结构。 在凹陷主体部分的表面部分之后，通过选择性地外延不同于剩余主体部分的半导体材料的半导体材料，在主体部分的剩余的物理暴露部分上形成异质外延通道部分。 可以在不同类型的半导体器件中形成多种类型的异质外延沟道部分。 可以在栅极腔中形成替代栅极结构，以提供具有不同阈值电压的场效应晶体管。

    FinFET HAVING SUPPRESSED LEAKAGE CURRENT
    63.
    发明申请
    FinFET HAVING SUPPRESSED LEAKAGE CURRENT 有权
    具有抑制漏电流的FinFET

    公开(公告)号：US20150145064A1

    公开(公告)日：2015-05-28

    申请号：US14087655

    申请日：2013-11-22

    Applicant: International Business Machines Corporation

    Inventor： Ravikumar Ramachandran ,  Henry K. Utomo ,  Reinaldo Vega

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

    CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

    Abstract: A FinFET device which includes: a semiconductor substrate; a three dimensional fin oriented perpendicularly to the semiconductor substrate; a local trench isolation between the three dimensional fin and an adjacent three dimensional fin; a nitride layer on the local trench isolation; a gate stack wrapped around a central portion of the three dimensional fin and extending through the nitride layer; sidewall spacers adjacent to the gate stack and indirectly in contact with the nitride layer, two ends of the three dimensional fin extending from the sidewall spacers, a first end being for the source of the FET device and a second end being for a drain of the FET device; and an epitaxial layer covering each end of the three dimensional fin and being on the nitride layer. Also disclosed is a method of fabricating a FinFET device.

    Abstract translation: 一种FinFET器件，包括：半导体衬底; 垂直于半导体衬底取向的三维鳍片; 三维翅片与相邻三维翅片之间的局部沟槽隔离; 局部沟槽隔离上的氮化物层; 围绕三维翅片的中心部分并延伸穿过氮化物层的栅极堆叠; 与栅叠层相邻并间接地与氮化物层接触的侧壁间隔件，三维鳍片的两端从侧壁间隔件延伸，第一端用于FET器件的源极，第二端用于漏极 FET器件; 以及覆盖三维翅片的每一端并且在氮化物层上的外延层。 还公开了一种制造FinFET器件的方法。

    REPLACEMENT METAL GATE STRUCTURES PROVIDING INDEPENDENT CONTROL ON WORK FUNCTION AND GATE LEAKAGE CURRENT
    65.
    发明申请
    REPLACEMENT METAL GATE STRUCTURES PROVIDING INDEPENDENT CONTROL ON WORK FUNCTION AND GATE LEAKAGE CURRENT 有权
    更换提供工作功能和门漏电流的独立控制的金属门结构

    公开(公告)号：US20130193522A1

    公开(公告)日：2013-08-01

    申请号：US13789018

    申请日：2013-03-07

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Unoh Kwon ,  Ramachandra Divakaruni ,  Siddarth A. Krishnan ,  Ravikumar Ramachandran

    IPC: H01L27/092

    CPC classification number: H01L27/092 ,  H01L21/28088 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/49 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843

    Abstract: The thickness and composition of a gate dielectric can be selected for different types of field effect transistors through a planar high dielectric constant material portion, which can be provided only for selected types of field effect transistors. Further, the work function of field effect transistors can be tuned independent of selection of the material stack for the gate dielectric. A stack of a barrier metal layer and a first-type work function metal layer is deposited on a gate dielectric layer within recessed gate cavities after removal of disposable gate material portions. After patterning the first-type work function metal layer, a second-type work function metal layer is deposited directly on the barrier metal layer in the regions of the second type field effect transistor. A conductive material fills the gate cavities, and a subsequent planarization process forms dual work function metal gate structures.

    Abstract translation: 可以通过平面高介电常数材料部分为不同类型的场效应晶体管选择栅极电介质的厚度和组成，其可以仅针对选定类型的场效应晶体管提供。 此外，场效应晶体管的工作功能可以独立于栅极电介质的材料堆叠的选择而被调整。 在去除一次性栅极材料部分之后，在凹入的栅极腔内的栅极电介质层上沉积阻挡金属层和第一类型功函数金属层的堆叠。 图案化第一型功函数金属层之后，第二类功函数金属层直接沉积在第二类型场效应晶体管的区域中的势垒金属层上。 导电材料填充栅极腔，随后的平坦化工艺形成双功能金属栅极结构。

    SELF-ALIGNED CONTACTS FOR HIGH k/METAL GATE PROCESS FLOW
    66.
    发明申请
    SELF-ALIGNED CONTACTS FOR HIGH k/METAL GATE PROCESS FLOW 有权
    用于高k /金属栅工艺流程的自对准接触

    公开(公告)号：US20130189834A1

    公开(公告)日：2013-07-25

    申请号：US13791520

    申请日：2013-03-08

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Ravikumar Ramachandran ,  Ramachandra Divakaruni ,  Ying Li

    IPC: H01L29/40

    CPC classification number: H01L29/401 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/49 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/6656

    Abstract: A semiconductor structure is provided that includes a semiconductor substrate having a plurality of gate stacks located thereon. Each gate stack includes a high k gate dielectric layer, a work function metal layer and a conductive metal. A spacer is located on sidewalls of each gate stack and a self-aligned dielectric liner is present on an upper surface of each spacer. A bottom surface of each self-aligned dielectric liner is present on an upper surface of a semiconductor metal alloy. A contact metal is located between neighboring gate stacks and is separated from each gate stack by the self-aligned dielectric liner. The structure also includes another contact metal having a portion that is located on and in direct contact with an upper surface of the contact metal and another portion that is located on and in direct contact with the conductive metal of one of the gate stacks.

    Abstract translation: 提供一种半导体结构，其包括具有位于其上的多个栅极叠层的半导体衬底。 每个栅极堆叠包括高k栅介质层，功函数金属层和导电金属。 间隔件位于每个栅极堆叠的侧壁上，并且自对准电介质衬垫存在于每个间隔件的上表面上。 每个自对准电介质衬垫的底表面存在于半导体金属合金的上表面上。 接触金属位于相邻的栅极堆叠之间，并通过自对准电介质衬垫与每个栅极堆叠分离。 该结构还包括另一个接触金属，其具有位于接触金属的上表面上且与触头金属的上表面直接接触的部分，以及位于与其中一个栅极叠层的导电金属直接接触的另一部分。

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