公开(公告)号：US10312157B2

公开(公告)日：2019-06-04

申请号：US15795414

申请日：2017-10-27

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

IPC: H01L27/092 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8238

Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.

公开(公告)号：US20180047639A1

公开(公告)日：2018-02-15

申请号：US15795413

申请日：2017-10-27

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

IPC: H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L27/092

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.

公开(公告)号：US09859169B2

公开(公告)日：2018-01-02

申请号：US14996572

申请日：2016-01-15

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

IPC: H01L21/8238 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.

公开(公告)号：US09768171B2

公开(公告)日：2017-09-19

申请号：US14970943

申请日：2015-12-16

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Siddarth A. Krishnan

IPC: H01L27/092 ,  H01L29/40 ,  H01L21/28 ,  H01L29/49 ,  H01L21/285 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/28088 ,  H01L21/28556 ,  H01L21/823842 ,  H01L29/401 ,  H01L29/4966

Abstract: A method of making a semiconductor device includes growing an interfacial layer on a substrate; depositing a first titanium nitride (TiN) layer on the interfacial layer; depositing a second TiN layer on the first TiN layer, the first TiN layer and the second TiN layer forming a bilayer work function gate stack of a first transistor; depositing a work function gate stack of a second transistor on the interfacial layer adjacent to the bilayer work function gate stack and on the bilayer work function stack; and depositing a gate electrode material on the work function gate stack of the second transistor.

公开(公告)号：US20160351452A1

公开(公告)日：2016-12-01

申请号：US15232895

申请日：2016-08-10

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Hemanth Jagannathan ,  Balaji Kannan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Rekha Rajaram

IPC: H01L21/8234 ,  H01L21/033 ,  H01L21/225 ,  H01L29/51 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L21/823462 ,  H01L21/02321 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/225 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28229 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3115 ,  H01L21/32115 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of fabricating advanced node field effect transistors using a replacement metal gate process. The method includes dopant a high-k dielectric directly or indirectly by using layers composed of multi-layer thin film stacks, or in other embodiments, by a single blocking layer. By taking advantage of unexpected etch selectivity of the multi-layer stack or the controlled etch process of a single layer stack, etch damage to the high-k may be avoided and work function metal thicknesses can be tightly controlled which in turn allows field effect transistors with low Tiny (inverse of gate capacitance) mismatch.

Abstract translation: 使用替代金属栅极工艺制造先进节点场效应晶体管的方法。 该方法通过使用由多层薄膜堆叠构成的层，或者在其它实施方案中通过单个阻挡层直接或间接地包括掺杂剂高k电介质。 通过利用多层堆叠的意想不到的蚀刻选择性或单层堆叠的受控蚀刻工艺，可以避免对高k的蚀刻损伤，并且可以严格控制功函数金属厚度，这又可以实现场效应晶体管 具有低Tiny（栅极电容的倒数）失配。

公开(公告)号：US09412658B2

公开(公告)日：2016-08-09

申请号：US14490792

申请日：2014-09-19

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Oleg Gluschenkov ,  Siddarth A. Krishnan ,  Joyeeta Nag ,  Andrew H. Simon ,  Shishir Ray

IPC: H01L23/52 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L21/4763

CPC classification number: H01L21/76894 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76867 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/00

Abstract: In-situ melting and crystallization of sealed cooper wires can be performed by means of laser annealing for a duration of nanoseconds. The intensity of the laser irradiation is selected such that molten copper wets interconnect interfaces, thereby forming an interfacial bonding arrangement that increases specular scattering of electrons. Nanosecond-scale temperature quenching preserves the formed interfacial bonding. At the same time, the fast crystallization process of sealed copper interconnects results in large copper grains, typically larger than 80 nm in lateral dimensions, on average. A typical duration of the annealing process is from about 10's to about 100's of nanoseconds. There is no degradation to interlayer low-k dielectric material despite the high anneal temperature due to ultra short duration that prevents collective motion of atoms within the dielectric material.

Abstract translation: 密封铜线的原位熔融和结晶可以通过激光退火进行纳秒的持续时间。 选择激光照射的强度，使得熔融铜浸润互连界面，从而形成增加电子的镜面散射的界面结合装置。 纳秒级温度淬火保持形成的界面结合。 同时，密封铜互连的快速结晶过程平均导致大的铜晶粒，通常大于80nm的横向尺寸。 退火过程的典型持续时间为约10秒至约100秒的纳秒。 尽管由于超短时间的高退火温度，层间低k介电材料没有劣化，从而防止原子在电介质材料内的集体运动。

公开(公告)号：US09330938B2

公开(公告)日：2016-05-03

申请号：US14340068

申请日：2014-07-24

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Hemanth Jagannathan ,  Balaji Kannan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Rekha Rajaram

IPC: H01L21/76 ,  H01L21/3213 ,  H01L21/28 ,  H01L21/321

CPC classification number: H01L21/823462 ,  H01L21/02321 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/225 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28229 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3115 ,  H01L21/32115 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of fabricating advanced node field effect transistors using a replacement metal gate process. The method includes dopant a high-k dielectric directly or indirectly by using layers composed of multi-layer thin film stacks, or in other embodiments, by a single blocking layer. By taking advantage of unexpected etch selectivity of the multi-layer stack or the controlled etch process of a single layer stack, etch damage to the high-k may be avoided and work function metal thicknesses can be tightly controlled which in turn allows field effect transistors with low Tinv (inverse of gate capacitance) mismatch.

Abstract translation: 使用替代金属栅极工艺制造先进节点场效应晶体管的方法。 该方法通过使用由多层薄膜堆叠构成的层，或者在其它实施方案中通过单个阻挡层直接或间接地包括掺杂剂高k电介质。 通过利用多层堆叠的意想不到的蚀刻选择性或单层堆叠的受控蚀刻工艺，可以避免对高k的蚀刻损伤，并且可以严格控制功函数金属厚度，这又可以实现场效应晶体管 具有低Tinv（栅极电容的倒数）不匹配。

公开(公告)号：US20160027664A1

公开(公告)日：2016-01-28

申请号：US14340068

申请日：2014-07-24

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Hemanth Jagannathan ,  Balaji Kannan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Rekha Rajaram

IPC: H01L21/3213 ,  H01L21/321 ,  H01L21/28

CPC classification number: H01L21/823462 ,  H01L21/02321 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/225 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28229 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3115 ,  H01L21/32115 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of fabricating advanced node field effect transistors using a replacement metal gate process. The method includes dopant a high-k dielectric directly or indirectly by using layers composed of multi-layer thin film stacks, or in other embodiments, by a single blocking layer. By taking advantage of unexpected etch selectivity of the multi-layer stack or the controlled etch process of a single layer stack, etch damage to the high-k may be avoided and work function metal thicknesses can be tightly controlled which in turn allows field effect transistors with low Tiny (inverse of gate capacitance) mismatch.

公开(公告)号：US20150145062A1

公开(公告)日：2015-05-28

申请号：US14088462

申请日：2013-11-25

Applicant: International Business Machines Corporation

Inventor： Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon

IPC: H01L29/06 ,  H01L21/8238 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/28 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L29/42376 ,  H01L21/28088 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/823807 ,  H01L21/82385 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of forming a semiconductor device includes forming first and second semiconductor structures on a semiconductor substrate. The first semiconductor structure includes a first gate channel region having a first gate length, and the second semiconductor structure including a second gate channel region having a second gate length that is greater than the first gate length. The method further includes depositing a work function metal layer in each of a first gate void formed at the first gate channel region and a second gate void formed at the second gate channel region. The method further includes depositing a semiconductor masking layer on the work function metal layer, and simultaneously etching the silicon masking layer located at the first and second gate channel regions to re-expose the first and second gate voids. A low-resistive metal is deposited in the first and second gate voids to form low-resistive metal gate stacks.

公开(公告)号：US10553498B2

公开(公告)日：2020-02-04

申请号：US15828822

申请日：2017-12-01

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Siddarth A. Krishnan

IPC: H01L21/70 ,  H01L21/8238 ,  H01L27/092

Abstract: A first aspect of the invention provides for a method including: forming an interfacial layer in a first opening in a pFET region and a second opening in an nFET region, each opening being in a dielectric layer in the pFET region and the nFET region; forming a high-k layer over the interfacial layer in each of the first and second openings; forming a wetting layer over the high-k layer in each of the first and second openings; forming a first metal layer in each of the first and second openings, the first metal layer including tungsten; and forming a first gate electrode layer over the first metal layer to substantially fill each of the first and second openings, thereby forming a first replacement gate stack over the pFET region and a second replacement gate stack over the nFET region.