公开(公告)号：US10546918B2

公开(公告)日：2020-01-28

申请号：US16537268

申请日：2019-08-09

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Joshua M. Rubin ,  Oscar Van Der Straten ,  Praneet Adusumilli

IPC: H01L49/02 ,  H01L29/66 ,  H01L23/522 ,  H01L27/11507 ,  H01L27/11502 ,  H01L27/108

Abstract: Metal-on-metal insulator structures and methods for making the same. The method includes: providing an insulator layer overlying a semiconductor substrate, forming a plurality of alternating first conductive layers and second conductive layers on the insulator layer, forming at least one dielectric layer between each of the alternating first conductive layers and second conductive layers, forming a first trench at a first location through a first portion of the plurality of the alternating first conductive layers and second conductive layers and the at least one dielectric layer, and first etching the first trench selective to the plurality of alternating first conductive layers and second conductive layers, wherein the first conductive layers are etched faster than the second conductive layers to form a first modified trench, wherein the first conductive layers are recessed relative to the center of the first modified trench greater than the second conductive layers.

公开(公告)号：US20190333983A1

公开(公告)日：2019-10-31

申请号：US15963406

申请日：2018-04-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Joshua M. Rubin ,  Son Nguyen

IPC: H01L49/02 ,  H01L21/768

Abstract: A semiconductor device includes a base structure including contacts and a first interlevel dielectric (ILD) layer, a metal-insulator metal (MIM) capacitor structure on the base structure, a second ILD layer on the MIM capacitor structure, and a plurality of vias including a first via on a first one of the contacts and penetrating through the first and second ILD layers, first and third etch tuning layers of the MIM capacitor structure and a second plate of the MIM capacitor structure, and a second via on a second one of the contacts and penetrating through the first and second ILD layers, a second etch tuning layer of the MIM capacitor structure, and first and third plates of the MIM capacitor structure.

公开(公告)号：US10332959B2

公开(公告)日：2019-06-25

申请号：US15364573

申请日：2016-11-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Terence B. Hook ,  Joshua M. Rubin ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/49 ,  H01L21/84 ,  H01L27/12 ,  H01L21/02

Abstract: A method for forming a semiconductor device comprises forming a fin in a bulk semiconductor substrate and depositing a first insulator layer over portions of the bulk semiconductor substrate adjacent to the fin. The method further includes removing portions of the first insulator layer to reduce a thickness of the first insulator layer and expose a sidewall of the fin. An etch stop layer is deposited on the first insulator layer. A gate stack is formed over a channel region of the fin and over portions of the etch stop layer. A portion of the bulk semiconductor substrate is removed to expose portions of the etch stop layer and the fin, and a second insulator layer is deposited over exposed portions of the fin and the etch stop layer.

公开(公告)号：US10103065B1

公开(公告)日：2018-10-16

申请号：US15496610

申请日：2017-04-25

Applicant: International Business Machines Corporation

Inventor： Shogo Mochizuki ,  Alexander Reznicek ,  Joshua M. Rubin ,  Junli Wang

IPC: H01L29/76 ,  H01L29/423 ,  H01L21/027 ,  H01L29/51 ,  H01L21/8234 ,  H01L21/033 ,  H01L27/12 ,  H01L29/78 ,  H01L29/165 ,  H01L21/265 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/786 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/78696

Abstract: Gate metal patterning techniques enable the incorporation of different work function metals in CMOS devices such as nanosheet transistor devices, vertical FETs, and FinFETs. Such techniques facilitate removal of gate metal from one region of a device without damage from over-etching to an adjacent region. The fabrication of CMOS devices with adjoining nFET/pFET gate structures and having very tight gate pitch is also facilitated. The techniques further enable the fabrication of CMOS devices with adjoining gate structures that require relatively long etch times for removal of gate metal therefrom, such as nanosheet transistors. A nanosheet transistor device including dual metal gates as fabricated allows tight integration.

公开(公告)号：US20180248042A1

公开(公告)日：2018-08-30

申请号：US15874308

申请日：2018-01-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Terence B. Hook ,  Joshua M. Rubin ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L21/8234 ,  H01L23/535 ,  H01L23/522

Abstract: A method of making a semiconductor device includes forming a plurality of fins on a substrate, with the substrate including an oxide layer arranged beneath the plurality of fins. A sacrificial gate material is deposited on and around the plurality of fins. First trenches are formed in the sacrificial gate material. The first trenches extend through the oxide layer to a top surface of the substrate and are arranged between fins of the plurality of fin. First trenches are filled with a metal gate stack. Second trenches are formed in the sacrificial gate material, with a bottom surface of the second trenches being arranged over a bottom surface of the first trenches, and the second trenches being arranged between fins of the plurality of fins and alternating with the first trenches. The second trenches are filled with a metal gate stack.

公开(公告)号：US09853151B2

公开(公告)日：2017-12-26

申请号：US14856918

申请日：2015-09-17

Applicant: International Business Machines Corporation

Inventor： Joshua M. Rubin ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L21/768 ,  H01L29/40 ,  H01L29/49

CPC classification number: H01L29/7845 ,  H01L21/02063 ,  H01L21/28525 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76865 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53271 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of making a semiconductor device includes forming a source/drain region on a substrate; disposing a gate stack on the substrate and adjacent to the source/drain region, the gate stack including a gate spacer along a sidewall of the gate stack; disposing an inter-level dielectric (ILD) layer on the source/drain region and the gate stack; removing a portion of the ILD layer on the source/drain region to form a source/drain contact pattern; filling the source/drain contact pattern with a layer of silicon material, the layer of silicon material being in contact with the source/drain region and in contact with the gate spacer; depositing a metallic layer over the first layer of silicon material; and performing a silicidation process to form a source/drain contact including a silicide.

公开(公告)号：US20170294507A1

公开(公告)日：2017-10-12

申请号：US15364578

申请日：2016-11-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Terence B. Hook ,  Joshua M. Rubin ,  Tenko Yamashita

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L21/762 ,  H01L29/10 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L29/0649 ,  H01L21/02642 ,  H01L21/76254 ,  H01L21/76256 ,  H01L21/76283 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1604 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method for forming a semiconductor device comprises forming a fin in a bulk semiconductor substrate and depositing a first insulator layer over portions of the bulk semiconductor substrate adjacent to the fin. The method further includes removing portions of the first insulator layer to reduce a thickness of the first insulator layer and expose a sidewall of the fin. An etch stop layer is deposited on the first insulator layer. A gate stack is formed over a channel region of the fin and over portions of the etch stop layer. A portion of the bulk semiconductor substrate is removed to expose portions of the etch stop layer and the fin, and a second insulator layer is deposited over exposed portions of the fin and the etch stop layer.

公开(公告)号：US20170294340A1

公开(公告)日：2017-10-12

申请号：US15091866

申请日：2016-04-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Terence B. Hook ,  Joshua M. Rubin ,  Tenko Yamashita

IPC: H01L21/762 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/0649 ,  H01L21/02642 ,  H01L21/76254 ,  H01L21/76256 ,  H01L21/76283 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1604 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method for forming a semiconductor device comprises forming a fin in a bulk semiconductor substrate and depositing a first insulator layer over portions of the bulk semiconductor substrate adjacent to the fin. The method further includes removing portions of the first insulator layer to reduce a thickness of the first insulator layer and expose a sidewall of the fin. An etch stop layer is deposited on the first insulator layer. A gate stack is formed over a channel region of the fin and over portions of the etch stop layer. A portion of the bulk semiconductor substrate is removed to expose portions of the etch stop layer and the fin, and a second insulator layer is deposited over exposed portions of the fin and the etch stop layer.

公开(公告)号：US09786546B1

公开(公告)日：2017-10-10

申请号：US15091866

申请日：2016-04-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Terence B. Hook ,  Joshua M. Rubin ,  Tenko Yamashita

IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/0649 ,  H01L21/02642 ,  H01L21/76254 ,  H01L21/76256 ,  H01L21/76283 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1604 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method for forming a semiconductor device comprises forming a fin in a bulk semiconductor substrate and depositing a first insulator layer over portions of the bulk semiconductor substrate adjacent to the fin. The method further includes removing portions of the first insulator layer to reduce a thickness of the first insulator layer and expose a sidewall of the fin. An etch stop layer is deposited on the first insulator layer. A gate stack is formed over a channel region of the fin and over portions of the etch stop layer. A portion of the bulk semiconductor substrate is removed to expose portions of the etch stop layer and the fin, and a second insulator layer is deposited over exposed portions of the fin and the etch stop layer.

公开(公告)号：US09741684B2

公开(公告)日：2017-08-22

申请号：US14827789

申请日：2015-08-17

Applicant: International Business Machines Corporation

Inventor： Joshua M. Rubin

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L24/83 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53228 ,  H01L25/00 ,  H01L2224/8303 ,  H01L2224/83896

Abstract: Wafer bonding edge protection techniques are provided. In one aspect, a method of forming Cu interconnects in a wafer includes: forming a dielectric layer on the wafer; forming a first mask on the dielectric layer; patterning the first mask with a footprint/location of the Cu interconnects, wherein the patterning of the first mask is performed over an entire surface of the wafer; forming a second mask on the first mask, wherein the second mask covers a portion of the patterned first mask at an edge region of the wafer; patterning trenches in the dielectric layer through the first mask and the second mask, wherein the second mask blocks formation of the trenches at the edge region of the wafer and thereby provides edge protection during patterning of the trenches; and forming the Cu interconnects in the trenches. A wafer bonding method and interconnect structure are also provided.