公开(公告)号：US10141203B2

公开(公告)日：2018-11-27

申请号：US15827199

申请日：2017-11-30

Applicant: General Electric Company

Inventor： Paul Alan McConnelee ,  Arun Virupaksha Gowda

IPC: H01L29/74 ,  H01L31/111 ,  H01L23/053 ,  H01L23/12 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L25/16 ,  H01L25/00 ,  H01L23/14 ,  H01L23/31 ,  H01L25/10

Abstract: An electronics package includes a lower insulating layer, an upper insulating layer coupled to the lower insulating layer, and a conductive contact pad coupled to a second surface of the upper insulating layer. An electrical component is positioned within an opening formed through the upper insulating layer. A first interconnect layer extends through at least one via in the lower insulating layer to electrically couple with at least one contact pad on the electrical component and a second interconnect layer extends through at least one via in the upper insulating layer and electrically couples the first interconnect layer to the conductive contact pad.

公开(公告)号：US20180130732A1

公开(公告)日：2018-05-10

申请号：US15343276

申请日：2016-11-04

Applicant: General Electric Company

Inventor： Risto Ilkka Tuominen ,  Arun Virupaksha Gowda

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: An electronics package includes an insulating substrate and an electrical component coupled to a first surface of the insulating substrate. A first conductor is formed on a second surface of the insulating substrate and extends through a first via therein to electrically couple with a first contact pad of the electrical component. A second conductor is formed on the second surface of the insulating substrate and extends through a second via therein to electrically couple with a second contact pad of the electrical component. The second conductor has a thickness greater than a thickness of the first conductor layer.

公开(公告)号：US20180130731A1

公开(公告)日：2018-05-10

申请号：US15343270

申请日：2016-11-04

Applicant: General Electric Company

Inventor： Risto Ilkka Tuominen ,  Arun Virupaksha Gowda

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/9212 ,  H01L2224/92144 ,  H01L2924/13055 ,  H01L2924/143 ,  H01L2924/1431 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An electronics package includes an insulating substrate, an electrical component coupled to a first surface of the insulating substrate, and a stepped conductor layer formed on a second surface of the insulating substrate, opposite the first surface. The stepped conductor layer includes a first portion that extends into at least one via formed through the insulating substrate to electrically couple with at least one contact pad of the electrical component and a second portion spaced away from the at least one via, the second portion having a thickness greater than the first portion.

公开(公告)号：US09966371B1

公开(公告)日：2018-05-08

申请号：US15343252

申请日：2016-11-04

Applicant: General Electric Company

Inventor： Risto Ilkka Tuominen ,  Arun Virupaksha Gowda

IPC: H01L23/48 ,  H01L23/52 ,  H01L25/00 ,  H01L23/498 ,  H01L25/065 ,  H01L21/48

CPC classification number: H01L25/50 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49844 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/08235 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/13339 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81801 ,  H01L2224/8184 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/8309 ,  H01L2224/83091 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/83865 ,  H01L2224/83874 ,  H01L2224/92144 ,  H01L2224/9222 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1302 ,  H01L2924/13023 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/143 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/82

Abstract: An electronics package includes an insulating substrate, a first electrical component coupled to a first surface of the insulating substrate, and a first conductor layer formed on the first surface of the insulating substrate. A second conductor layer is formed on a second surface of the insulating substrate, opposite the first surface, the second conductor layer extending through vias in the insulating substrate to contact at least one contact pad of the first electrical component and couple with the first conductor layer. The electronics package also includes a second electrical component having at least one contact pad coupled to the first conductor layer. The first conductor layer has a thickness greater than a thickness of the second conductor layer.

公开(公告)号：US09953913B1

公开(公告)日：2018-04-24

申请号：US15375771

申请日：2016-12-12

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Raymond Albert Fillion ,  Paul Alan McConnelee

IPC: H01L23/04 ,  H01L23/498 ,  H01L23/31 ,  H01L23/66 ,  H01L21/48 ,  H01L21/56 ,  H01L23/373 ,  H01L25/07 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/66 ,  H01L24/05 ,  H01L24/32 ,  H01L25/072 ,  H01L2224/32245 ,  H01L2924/10253 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19043

Abstract: An electronics package includes an insulating substrate, a semiconductor device having a top surface coupled to a first side of the insulating substrate, and a pass-through component coupled to the first side of the insulating substrate. The pass-through component includes an insulating core and at least one through-hole structure comprising a conductive body extending through the thickness of the insulating core. A metallization layer is formed on a second side of the insulating substrate and extends through at least one via in the insulating substrate to electrically couple at least one conductive pad on the top surface of the semiconductor device to the at least one through-hole structure. An insulating material surrounds the semiconductor device and the insulating core of the pass-through component.

公开(公告)号：US20170250093A1

公开(公告)日：2017-08-31

申请号：US15594794

申请日：2017-05-15

Applicant: General Electric Company

Inventor： Paul Alan McConnelee ,  Arun Virupaksha Gowda

IPC: H01L21/56 ,  H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L23/14 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/561 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/76897 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/538 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/09 ,  H01L24/19 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/83865 ,  H01L2224/83874 ,  H01L2224/83895 ,  H01L2224/83931 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/20 ,  H01L2924/014 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00012

Abstract: An electronics package includes a lower insulating layer, an upper insulating layer coupled to the lower insulating layer, and a conductive contact pad coupled to a second surface of the upper insulating layer. An electrical component is positioned within an opening formed through the upper insulating layer. A first interconnect layer extends through at least one via in the lower insulating layer to electrically couple with at least one contact pad on the electrical component and a second interconnect layer extends through at least one via in the upper insulating layer and electrically couples the first interconnect layer to the conductive contact pad.

公开(公告)号：US09570376B2

公开(公告)日：2017-02-14

申请号：US14625744

申请日：2015-02-19

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Kevin Matthew Durocher ,  Scott Smith ,  Donald Paul Cunningham

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/92144 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/00

Abstract: A chip package includes a first substrate having at least one circuit layer formed on a first surface thereof, a first die mounted on a second surface of the first substrate opposite from the first surface, and an interconnection assembly comprising upper and lower conductive layers provided on an insulating substrate, with the upper conductive layer of the interconnection assembly affixed to the second surface of the first substrate and electrically connected to the at least one circuit layer of the first substrate. A second substrate is positioned on a side of the first die opposite from the first substrate so as to position the die between the first and second substrates, the second substrate having at least one circuit layer formed on an outward facing first surface thereof that is electrically connected to at least one of the lower conductive layers of the interconnection assembly and the first die.

Abstract translation: 芯片封装包括：第一基板，其具有在其第一表面上形成的至少一个电路层，安装在第一基板的与第一表面相对的第二表面上的第一裸片;以及互连组件，其包括设置在第一基板上的上下导电层 绝缘基板，其中互连组件的上导电层固定到第一基板的第二表面并电连接到第一基板的至少一个电路层。 第二基板位于与第一基板相对的第一模具的一侧上，以便将模具定位在第一和第二基板之间，第二基板具有形成在其面向外的第一表面上的至少一个电路层， 连接到互连组件和第一模具的至少一个下导电层。

公开(公告)号：US20160056136A1

公开(公告)日：2016-02-25

申请号：US14464877

申请日：2014-08-21

Applicant: General Electric Company

Inventor： Paul Alan McConnelee ,  Arun Virupaksha Gowda

IPC: H01L25/16 ,  H01L23/00 ,  H01L21/768 ,  H01L23/538 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L21/561 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/76897 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/538 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/09 ,  H01L24/19 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/83865 ,  H01L2224/83874 ,  H01L2224/83895 ,  H01L2224/83931 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/20 ,  H01L2924/014 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00012

Abstract: An electronics package includes a first dielectric substrate having a first plurality of vias formed through a thickness thereof, a metalized contact layer coupled to a top surface of the first dielectric substrate, and a first die positioned within a first die opening formed through the thickness of the first dielectric substrate. Metalized interconnects are formed on a bottom surface of the first dielectric substrate and extend through the first plurality of vias to contact the metalized contact layer. A second dielectric substrate is coupled to the first dielectric substrate and has a second plurality of vias formed through a thickness thereof. Metalized interconnects extend through the second plurality of vias to contact the first plurality of metalized interconnects and contact pads of the first die. A first conductive element electrically couples the first die to the metalized contact layer.

Abstract translation: 一种电子封装包括：第一介电基片，具有通过其厚度形成的第一多个通孔;金属化接触层，其耦合到第一电介质基板的顶表面;以及第一裸片，位于第一裸片开口内， 第一电介质基片。 金属化互连件形成在第一电介质基片的底表面上并延伸通过第一多个通孔以接触金属化的接触层。 第二电介质基板耦合到第一电介质基板，并且具有通过其厚度形成的第二多个通孔。 金属化互连延伸穿过第二多个通孔以接触第一裸片的第一多个金属化互连和接触垫。 第一导电元件将第一裸片电耦合到金属化接触层。

公开(公告)号：US20150287699A1

公开(公告)日：2015-10-08

申请号：US14742773

申请日：2015-06-18

Applicant: General Electric Company

Inventor： Paul Alan McConnelee ,  Arun Virupaksha Gowda

IPC: H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6836 ,  H01L23/49822 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/2101 ,  H01L2224/221 ,  H01L2224/27003 ,  H01L2224/27312 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/2741 ,  H01L2224/27416 ,  H01L2224/27418 ,  H01L2224/27422 ,  H01L2224/27436 ,  H01L2224/2781 ,  H01L2224/27848 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2224/94 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/3511 ,  H05K3/305 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2224/19 ,  H01L21/78 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A chip package includes a first die with an active surface having at least one die pad positioned thereon; a first adhesive layer having a first surface coupled to the active surface of the first die and a second surface opposite the first surface; and a first dielectric layer having a top surface. A first portion of the top surface of the first dielectric layer is coupled to the second surface of the first adhesive layer. A second portion of the top surface of the first dielectric layer, distinct from the first portion, is substantially free of adhesive.

Abstract translation: 芯片封装包括具有活性表面的第一裸片，其中至少一个芯片焊盘位于其上; 第一粘合剂层，其具有联接到第一管芯的有效表面的第一表面和与第一表面相对的第二表面; 以及具有顶表面的第一电介质层。 第一电介质层的顶表面的第一部分耦合到第一粘合剂层的第二表面。 与第一部分不同的第一介电层的顶表面的第二部分基本上没有粘合剂。

公开(公告)号：US20150171036A1

公开(公告)日：2015-06-18

申请号：US14625744

申请日：2015-02-19

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Kevin Matthew Durocher ,  Scott Smith ,  Donald Paul Cunningham

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L23/481 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/92144 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/00

Abstract: A chip package includes a first substrate having at least one circuit layer formed on a first surface thereof, a first die mounted on a second surface of the first substrate opposite from the first surface, and an interconnection assembly comprising upper and lower conductive layers provided on an insulating substrate, with the upper conductive layer of the interconnection assembly affixed to the second surface of the first substrate and electrically connected to the at least one circuit layer of the first substrate. A second substrate is positioned on a side of the first die opposite from the first substrate so as to position the die between the first and second substrates, the second substrate having at least one circuit layer formed on an outward facing first surface thereof that is electrically connected to at least one of the lower conductive layers of the interconnection assembly and the first die.

Abstract translation: 芯片封装包括：第一基板，其具有在其第一表面上形成的至少一个电路层，安装在第一基板的与第一表面相对的第二表面上的第一裸片;以及互连组件，其包括设置在第一基板上的上下导电层 绝缘基板，其中互连组件的上导电层固定到第一基板的第二表面并电连接到第一基板的至少一个电路层。 第二基板位于与第一基板相对的第一模具的一侧上，以便将模具定位在第一和第二基板之间，第二基板具有形成在其面向外的第一表面上的至少一个电路层， 连接到互连组件和第一模具的至少一个下导电层。