公开(公告)号：US10804115B2

公开(公告)日：2020-10-13

申请号：US15668502

申请日：2017-08-03

Applicant: General Electric Company

Inventor： Christopher James Kapusta ,  Raymond Albert Fillion ,  Risto Ilkka Sakari Tuominen ,  Kaustubh Ravindra Nagarkar

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/52 ,  H01L23/31 ,  H01L23/28 ,  H01L23/16 ,  H01L23/00 ,  H01L23/538 ,  H01L23/50

Abstract: An electronics package includes an insulating substrate, an electrical component having an active surface coupled to a first surface of the insulating substrate, and an insulating structure disposed adjacent the electrical component on the first surface of the insulating substrate. A first wiring layer is formed on a top surface of the insulating structure and extends down at least one sloped side surface of the insulating structure. A second wiring layer is formed on a second surface of the insulating substrate. The second wiring layer extends through a plurality of vias in the insulating substrate to electrically couple at least one contact pad on the active surface of the electrical component to the first wiring layer.

公开(公告)号：US20200066544A1

公开(公告)日：2020-02-27

申请号：US16667018

申请日：2019-10-29

Applicant: General Electric Company

Inventor： Christopher James Kapusta ,  Raymond Albert Fillion ,  Risto Ilkka Sakari Tuominen ,  Kaustubh Ravindra Nagarkar

IPC: H01L21/48 ,  H01L27/146 ,  H01L23/00 ,  H01L27/14 ,  H01L23/367 ,  H01L23/31 ,  H01L23/14 ,  H01L23/28 ,  H01L21/52 ,  H01L21/56

Abstract: An electronics package includes an insulating substrate, an electrical component having a back surface coupled to a first surface of the insulating substrate, and an insulating structure surrounding at least a portion of a perimeter of the electrical component. A first wiring layer extends from the first surface of the insulating substrate and over a sloped side surface of the insulating structure to electrically couple with at least one contact pad on an active surface of the electrical component. A second wiring layer is formed on a second surface of the insulating substrate and extends through at least one via therein to electrically couple with the first wiring layer.

公开(公告)号：US10541209B2

公开(公告)日：2020-01-21

申请号：US15668553

申请日：2017-08-03

Applicant: General Electric Company

Inventor： Christopher James Kapusta ,  Raymond Albert Fillion ,  Risto Ilkka Sakari Tuominen ,  Kaustubh Ravindra Nagarkar

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/52 ,  H01L23/28 ,  H01L23/552

Abstract: An electronics package includes a support substrate, an electrical component having a first surface coupled to a first surface of the support substrate, and an insulating structure coupled to the first surface of the support substrate and sidewalls of the electrical component. The insulating structure has a sloped outer surface. A conductive layer encapsulates the electrical component and the sloped outer surface of the insulating structure. A first wiring layer is formed on a second surface of the support substrate. The first wiring layer is coupled to the conductive layer through at least one via in the support substrate.

公开(公告)号：US10276523B1

公开(公告)日：2019-04-30

申请号：US15816312

申请日：2017-11-17

Applicant: General Electric Company

Inventor： Raymond Albert Fillion ,  Kaustubh Ravindra Nagarkar

IPC: H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L23/31

Abstract: A reconfigured semiconductor device includes a semiconductor device comprising an active surface having a plurality of input/output (I/O) pads spaced at a non-solderable pitch thereon and at least one redistribution layer overlying the active surface of the semiconductor device. Each at least one redistribution layer includes an insulating layer and a patterned conductive layer comprising a plurality of discrete terminal pads formed on the insulating layer, each of the plurality of discrete terminal pads electrically coupled to a respective I/O pad of the plurality of I/O pads by a conductive via formed through the insulating layer.

公开(公告)号：US20190043810A1

公开(公告)日：2019-02-07

申请号：US15668553

申请日：2017-08-03

Applicant: General Electric Company

Inventor： Christopher James Kapusta ,  Raymond Albert Fillion ,  Risto Ilkka Sakari Tuominen ,  Kaustubh Ravindra Nagarkar

IPC: H01L23/552 ,  H01L21/52 ,  H01L21/56 ,  H01L21/48

Abstract: An electronics package includes a support substrate, an electrical component having a first surface coupled to a first surface of the support substrate, and an insulating structure coupled to the first surface of the support substrate and sidewalls of the electrical component. The insulating structure has a sloped outer surface. A conductive layer encapsulates the electrical component and the sloped outer surface of the insulating structure. A first wiring layer is formed on a second surface of the support substrate. The first wiring layer is coupled to the conductive layer through at least one via in the support substrate.

公开(公告)号：US09953913B1

公开(公告)日：2018-04-24

申请号：US15375771

申请日：2016-12-12

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Raymond Albert Fillion ,  Paul Alan McConnelee

IPC: H01L23/04 ,  H01L23/498 ,  H01L23/31 ,  H01L23/66 ,  H01L21/48 ,  H01L21/56 ,  H01L23/373 ,  H01L25/07 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/66 ,  H01L24/05 ,  H01L24/32 ,  H01L25/072 ,  H01L2224/32245 ,  H01L2924/10253 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19043

Abstract: An electronics package includes an insulating substrate, a semiconductor device having a top surface coupled to a first side of the insulating substrate, and a pass-through component coupled to the first side of the insulating substrate. The pass-through component includes an insulating core and at least one through-hole structure comprising a conductive body extending through the thickness of the insulating core. A metallization layer is formed on a second side of the insulating substrate and extends through at least one via in the insulating substrate to electrically couple at least one conductive pad on the top surface of the semiconductor device to the at least one through-hole structure. An insulating material surrounds the semiconductor device and the insulating core of the pass-through component.

公开(公告)号：US20200066652A1

公开(公告)日：2020-02-27

申请号：US16667376

申请日：2019-10-29

Applicant: General Electric Company

Inventor： Christopher James Kapusta ,  Raymond Albert Fillion ,  Risto Ilkka Sakari Tuominen ,  Kaustubh Ravindra Nagarkar

IPC: H01L23/552 ,  H01L21/52 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00

Abstract: An electronics package includes a support substrate, an electrical component having a first surface coupled to a first surface of the support substrate, and an insulating structure coupled to the first surface of the support substrate and sidewalls of the electrical component. The insulating structure has a sloped outer surface. A conductive layer encapsulates the electrical component and the sloped outer surface of the insulating structure. A first wiring layer is formed on a second surface of the support substrate. The first wiring layer is coupled to the conductive layer through at least one via in the support substrate.

公开(公告)号：US20190304910A1

公开(公告)日：2019-10-03

申请号：US15943855

申请日：2018-04-03

Applicant: General Electric Company

Inventor： Raymond Albert Fillion

IPC: H01L23/528 ,  H01L27/088 ,  H03K19/0175 ,  H01L23/498 ,  H01L21/768 ,  H01L21/48 ,  H01L23/50 ,  H01L23/58

Abstract: An embedded electronics package and method of manufacture includes a support substrate, a power semiconductor component coupled to a first side of the support substrate, and a logic semiconductor component coupled to a second side of the support substrate, opposite the first side. A first insulating material surrounds the logic semiconductor component. A logic interconnect layer is electrically coupled to the logic semiconductor component by at least one conductive micro-via extending through a portion of the first insulating material. A power interconnect layer is electrically coupled to the power semiconductor component by at least one conductive macro-via extending through a thickness of the support substrate. The power interconnect layer is thicker than the logic interconnect layer.

公开(公告)号：US10396053B2

公开(公告)日：2019-08-27

申请号：US15816396

申请日：2017-11-17

Applicant: General Electric Company

Inventor： Raymond Albert Fillion ,  Kaustubh Ravindra Nagarkar

IPC: H01L23/00 ,  H01L23/50

Abstract: A reconfigured semiconductor logic device includes a semiconductor logic device comprising an active surface having a plurality of input/output (I/O) pads formed thereon and a redistribution layer. The redistribution layer includes an insulating layer disposed on the active surface of the semiconductor logic device and a patterned conductive layer comprising a plurality of discrete terminal pads formed atop the insulating layer. The plurality of discrete terminal pads are electrically coupled to respective I/O pads of the plurality of I/O pads by conductive vias formed through the insulating layer. The plurality of discrete terminal pads are larger than the plurality of I/O pads.

公开(公告)号：US20190157233A1

公开(公告)日：2019-05-23

申请号：US15816396

申请日：2017-11-17

Applicant: General Electric Company

Inventor： Raymond Albert Fillion ,  Kaustubh Ravindra Nagarkar

IPC: H01L23/00 ,  H01L23/50

CPC classification number: H01L24/20 ,  H01L23/50 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L24/19 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/0603 ,  H01L2224/06131 ,  H01L2224/13024 ,  H01L2224/211 ,  H01L2924/1431 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/37001

Abstract: A reconfigured semiconductor logic device includes a semiconductor logic device comprising an active surface having a plurality of input/output (I/O) pads formed thereon and a redistribution layer. The redistribution layer includes an insulating layer disposed on the active surface of the semiconductor logic device and a patterned conductive layer comprising a plurality of discrete terminal pads formed atop the insulating layer. The plurality of discrete terminal pads are electrically coupled to respective I/O pads of the plurality of I/O pads by conductive vias formed through the insulating layer. The plurality of discrete terminal pads are larger than the plurality of I/O pads.