公开(公告)号：US10541153B2

公开(公告)日：2020-01-21

申请号：US15668468

申请日：2017-08-03

Applicant: General Electric Company

Inventor： Christopher James Kapusta ,  Raymond Albert Fillion ,  Risto Ilkka Sakari Tuominen ,  Kaustubh Ravindra Nagarkar

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/52 ,  H01L23/28 ,  H01L23/31

Abstract: An electronics package includes an insulating substrate, an electrical component having a back surface coupled to a first surface of the insulating substrate, and an insulating structure surrounding at least a portion of a perimeter of the electrical component. A first wiring layer extends from the first surface of the insulating substrate and over a sloped side surface of the insulating structure to electrically couple with at least one contact pad on an active surface of the electrical component. A second wiring layer is formed on a second surface of the insulating substrate and extends through at least one via therein to electrically couple with the first wiring layer.

公开(公告)号：US20190043794A1

公开(公告)日：2019-02-07

申请号：US15668522

申请日：2017-08-03

Applicant: General Electric Company

Inventor： Christopher James Kapusta ,  Risto Ilkka Sakari Tuominen ,  Kaustubh Ravindra Nagarkar ,  Raymond Albert Fillion

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: An electronics package includes a support substrate, an electrical component having an active surface coupled to a first surface of the support substrate, and an insulating structure coupled to the first surface of the support substrate and at least one side wall of the electrical component. A functional layer comprising at least one functional component is formed on at least one of a sloped side wall of the insulating structure and a backside surface of the electrical component. A first wiring layer is formed on a second surface of the support substrate. The first wiring layer is electrically coupled to the functional layer through at least one via in the support substrate.

公开(公告)号：US10957832B2

公开(公告)日：2021-03-23

申请号：US16166313

申请日：2018-10-22

Applicant: General Electric Company

Inventor： Christopher James Kapusta ,  Risto Ilkka Sakari Tuominen ,  Kaustubh Ravindra Nagarkar

IPC: H01L33/62 ,  H01L23/538 ,  H01L33/54 ,  H01L33/60 ,  H01L25/075 ,  H01L25/16 ,  H01L33/64

Abstract: A light emitting semiconductor (LES) device having desirable thermal performance characteristics is disclosed. The LES device includes an insulating substrate layer having a plurality of vias formed therein and at least one LES chip mounted on the insulating substrate layer, with each of the LES chips(s) including an active surface including a light emitting area configured to emit light therefrom and a back surface positioned on a top surface of the insulating substrate layer and including connection pads thereon. A conductor layer is positioned on a bottom surface of the insulating substrate layer and in the vias, the conductor layer in direct contact with the connection pads of the LES chip(s) so as to be electrically and thermally connected thereto. An encapsulant is positioned adjacent the top surface of the insulating substrate layer and surrounding at least part of the LES chip(s), the encapsulant comprising a light transmitting material.

公开(公告)号：US20200066652A1

公开(公告)日：2020-02-27

申请号：US16667376

申请日：2019-10-29

Applicant: General Electric Company

Inventor： Christopher James Kapusta ,  Raymond Albert Fillion ,  Risto Ilkka Sakari Tuominen ,  Kaustubh Ravindra Nagarkar

IPC: H01L23/552 ,  H01L21/52 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00

Abstract: An electronics package includes a support substrate, an electrical component having a first surface coupled to a first surface of the support substrate, and an insulating structure coupled to the first surface of the support substrate and sidewalls of the electrical component. The insulating structure has a sloped outer surface. A conductive layer encapsulates the electrical component and the sloped outer surface of the insulating structure. A first wiring layer is formed on a second surface of the support substrate. The first wiring layer is coupled to the conductive layer through at least one via in the support substrate.

公开(公告)号：US20190043733A1

公开(公告)日：2019-02-07

申请号：US15668468

申请日：2017-08-03

Applicant: General Electric Company

Inventor： Christopher James Kapusta ,  Raymond Albert Fillion ,  Risto Ilkka Sakari Tuominen ,  Kaustubh Ravindra Nagarkar

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/52 ,  H01L23/28 ,  H01L23/31

Abstract: An electronics package includes an insulating substrate, an electrical component having a back surface coupled to a first surface of the insulating substrate, and an insulating structure surrounding at least a portion of a perimeter of the electrical component. A first wiring layer extends from the first surface of the insulating substrate and over a sloped side surface of the insulating structure to electrically couple with at least one contact pad on an active surface of the electrical component. A second wiring layer is formed on a second surface of the insulating substrate and extends through at least one via therein to electrically couple with the first wiring layer.

公开(公告)号：US20240266270A1

公开(公告)日：2024-08-08

申请号：US18166192

申请日：2023-02-08

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Ljubisa D. Stevanovic ,  Christopher James Kapusta ,  Robert Dwayne Gossman ,  Risto Ilkka Sakari Tuominen

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L23/49861

Abstract: A semiconductor assembly includes a semiconductor device and a POL-RDL package coupled to said device. The device includes an upper surface, a gate pad and at least one source pad disposed on said upper surface. The POL-RDL package includes a dielectric layer having at least one source pad electrically coupled to said at least one source pad of said device and at least one contact pad disposed. At least one trace connection having a resistivity value electrically couples said at least one source pad of said POL-RDL package to said at least one contact pad.

公开(公告)号：US10892231B2

公开(公告)日：2021-01-12

申请号：US16667376

申请日：2019-10-29

Applicant: General Electric Company

Inventor： Christopher James Kapusta ,  Raymond Albert Fillion ,  Risto Ilkka Sakari Tuominen ,  Kaustubh Ravindra Nagarkar

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/52 ,  H01L23/31 ,  H01L23/552 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

Abstract: An electronics package includes a support substrate, an electrical component having a first surface coupled to a first surface of the support substrate, and an insulating structure coupled to the first surface of the support substrate and sidewalls of the electrical component. The insulating structure has a sloped outer surface. A conductive layer encapsulates the electrical component and the sloped outer surface of the insulating structure. A first wiring layer is formed on a second surface of the support substrate. The first wiring layer is coupled to the conductive layer through at least one via in the support substrate.

公开(公告)号：US10332832B2

公开(公告)日：2019-06-25

申请号：US15670423

申请日：2017-08-07

Applicant: General Electric Company

Inventor： Christopher James Kapusta ,  Raymond Albert Fillion ,  Risto Ilkka Sakari Tuominen ,  Kaustubh Ravindra Nagarkar

IPC: H01L21/00 ,  H01L23/522 ,  H01L23/495 ,  H01L25/04 ,  H01L23/00 ,  H01L21/48

Abstract: A method of manufacturing a multi-layer electronics package includes attaching a base insulating substrate to a frame having an opening therein and such that the frame is positioned above and/or below the base insulating substrate to provide support thereto. A first conductive wiring layer is applied on the first side of the base insulating substrate, and vias are formed in the base insulating substrate. A second conductive wiring layer is formed on the second side of the base insulating substrate that covers the vias and the exposed portions of the first conductive wiring layer and at least one additional insulating substrate is bonded to the base insulating substrate. Vias are formed in each additional insulating substrate and an additional conductive wiring layer is formed on each of the additional insulating substrate. The described build-up forms a multilayer interconnect structure, with the frame providing support for this build-up.

公开(公告)号：US20250062280A1

公开(公告)日：2025-02-20

申请号：US18234603

申请日：2023-08-16

Applicant: General Electric Company

Inventor： Ljubisa D. Stevanovic ,  Arun Virupaksha Gowda ,  Christopher James Kapusta ,  Risto Ilkka Sakari Tuominen

IPC: H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L23/48

Abstract: A multi-chip semiconductor package includes a dielectric interconnect layer having an upper surface and a bottom surface, at least one common source pad disposed on the upper surface of the interconnect layer, at least one common gate pad disposed on the upper surface of the interconnect layer, and a plurality of semiconductor devices each including a gate pad and at least one source pad adhered onto the interconnect layer, wherein the source pads of the plurality of semiconductor devices are electrically connected to the at least one common source pad, and wherein the source pads of the plurality of semiconductor devices are electrically connected in parallel with one another, and wherein the gate pads of the plurality of semiconductor devices are electrically connected to the common gate pad, and wherein the gate pads of the plurality of semiconductor devices are electrically connected in parallel with one another.

公开(公告)号：US10804116B2

公开(公告)日：2020-10-13

申请号：US16667018

申请日：2019-10-29

Applicant: General Electric Company

Inventor： Christopher James Kapusta ,  Raymond Albert Fillion ,  Risto Ilkka Sakari Tuominen ,  Kaustubh Ravindra Nagarkar

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/52 ,  H01L23/28 ,  H01L23/31 ,  H01L23/14 ,  H01L23/00 ,  H01L23/367 ,  H01L27/14 ,  H01L27/146 ,  H01L23/42

Abstract: An electronics package includes an insulating substrate, an electrical component having a back surface coupled to a first surface of the insulating substrate, and an insulating structure surrounding at least a portion of a perimeter of the electrical component. A first wiring layer extends from the first surface of the insulating substrate and over a sloped side surface of the insulating structure to electrically couple with at least one contact pad on an active surface of the electrical component. A second wiring layer is formed on a second surface of the insulating substrate and extends through at least one via therein to electrically couple with the first wiring layer.