公开(公告)号：US20120097913A1

公开(公告)日：2012-04-26

申请号：US12909650

申请日：2010-10-21

Applicant: Jun Liu ,  John K. Zahurak

Inventor： Jun Liu ,  John K. Zahurak

IPC: H01L45/00 ,  H01L21/02

CPC classification number: H01L45/1266 ,  H01L21/28114 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2472 ,  H01L27/2481 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/6656 ,  H01L29/66621 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1691

Abstract: An integrated circuit has a nonvolatile memory cell that includes a first electrode, a second electrode, and an ion conductive material there-between. At least one of the first and second electrodes has an electrochemically active surface received directly against the ion conductive material. The second electrode is elevationally outward of the first electrode. The first electrode extends laterally in a first direction and the ion conductive material extends in a second direction different from and intersecting the first direction. The first electrode is received directly against the ion conductive material only where the first and second directions intersect. Other embodiments, including method embodiments, are disclosed.

Abstract translation: 集成电路具有包括第一电极，第二电极和离子导电材料的非易失性存储单元。 第一和第二电极中的至少一个具有直接接受离子导电材料接受的电化学活性表面。 第二电极位于第一电极的正上方。 第一电极在第一方向上横向延伸，并且离子导电材料沿与第一方向不同并与第一方向相交的第二方向延伸。 仅在第一和第二方向相交的情况下，第一电极直接接收在离子导电材料上。 公开了包括方法实施例的其他实施例。

公开(公告)号：US08134137B2

公开(公告)日：2012-03-13

申请号：US12141388

申请日：2008-06-18

Applicant: Jun Liu

Inventor： Jun Liu

IPC: H01L21/44

CPC classification number: H01L45/1608 ,  G11C13/003 ,  G11C2213/72 ,  H01L27/1021 ,  H01L27/24 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/6609 ,  H01L29/872

Abstract: Memory device constructions include a first column line extending parallel to a second column line, the first column line being above the second column line; a row line above the second column line and extending perpendicular to the first column line and the second column line; memory material disposed to be selectively and reversibly configured in one of two or more different resistive states; a first diode configured to conduct a first current between the first column line and the row line via the memory material; and a second diode configured to conduct a second current between the second column line and the row line via the memory material. In some embodiments, the first diode is a Schottky diode having a semiconductor anode and a metal cathode and the second diode is a Schottky diode having a metal anode and a semiconductor cathode.

Abstract translation: 存储器件结构包括平行于第二列线延伸的第一列线，第一列线在第二列线之上; 在第二列线上方的行线，并垂直于第一列线和第二列线延伸; 存储器材料，其设置成选择性地和可逆地配置为两种或更多种不同电阻状态之一; 第一二极管，被配置为经由所述存储材料在所述第一列线和所述行线之间传导第一电流; 以及第二二极管，被配置为经由存储器材料在第二列线和行线之间传导第二电流。 在一些实施例中，第一二极管是具有半导体阳极和金属阴极的肖特基二极管，第二二极管是具有金属阳极和半导体阴极的肖特基二极管。

公开(公告)号：US20120057391A1

公开(公告)日：2012-03-08

申请号：US13292680

申请日：2011-11-09

Applicant: Jun Liu

Inventor： Jun Liu

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0073 ,  G11C2013/009 ,  G11C2213/72 ,  G11C2213/74

Abstract: Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.

Abstract translation: 所公开的实施例包括存储器单元操作方法，存储单元编程方法，存储单元读取方法，存储单元和存储器件。 在一个实施例中，存储器单元包括字线，第一位线，第二位线和存储器元件。 存储元件电连接到字线并选择性地电连接到第一位线和第二位线。 存储元件经由存储元件的电阻状态存储信息。 存储器单元被配置为经由从第一位线通过存储器元件流向字线的第一电流或从字线通过存储器元件流向第二位线的第二电流来传送存储器元件的电阻状态。

公开(公告)号：US20120056146A1

公开(公告)日：2012-03-08

申请号：US13292884

申请日：2011-11-09

Applicant: Jun Liu ,  Mike Violette

Inventor： Jun Liu ,  Mike Violette

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/003 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

Abstract: A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.

Abstract translation: 电阻式存储器结构，例如相变存储器结构，包括一个存取器件和两个或更多个电阻存储器单元。 每个存储单元耦合到整流装置，以防止并行漏电流流过未选择的存储单元。 在电阻存储器位结构的阵列中，来自不同存储器位结构的电阻存储器单元被堆叠并共享整流器件。

公开(公告)号：US08102700B2

公开(公告)日：2012-01-24

申请号：US12242261

申请日：2008-09-30

Applicant: Jun Liu ,  Gurtej Sandhu

Inventor： Jun Liu ,  Gurtej Sandhu

IPC: G11C11/14 ,  G11C11/15 ,  G11C11/02

CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1695 ,  H01L43/02

Abstract: Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents.

Abstract translation: 配置为单向编程的自旋扭矩传递磁性随机存取存储器件以及编程这种器件的方法。 这些装置包括具有两个钉扎层和其间的自由层的存储单元。 通过利用两个固定层，分别从两个固定层中的每一个自由层上的自旋转矩效应允许以单向电流编程存储器单元。

公开(公告)号：US08102162B2

公开(公告)日：2012-01-24

申请号：US12482818

申请日：2009-06-11

Applicant: Zaki Moussaoui ,  Leigh Cormie ,  Jun Liu

Inventor： Zaki Moussaoui ,  Leigh Cormie ,  Jun Liu

IPC: G05F1/563

CPC classification number: H02M3/1582

Abstract: An integrated circuit controller for controlling the operation of a voltage converter which includes a first comparator for comparing a voltage associated with an input of a boost converter with a threshold voltage and generating a control signal in response thereto. A second comparator compares a second voltage associated with an output of the boost converter with the threshold voltage and generates a second control signal in response thereto. Driver circuitry generates a first switching transistor drive signal and a second switching transistor drive signal. The first switching transistor drive signal is used for driving an upper gate switching transistor of a buck converter. The second switching transistor drive signal may be configured in a first mode of operation to drive a lower gate switching transistor of the buck converter and may be configured in a second mode of operation to drive a switching transistor of the boost converter. Control logic enables/disables at least a portion of the driver circuitry responsive to the control signal and the second control signal.

Abstract translation: 一种用于控制电压转换器的操作的集成电路控制器，其包括用于将与升压转换器的输入相关联的电压与阈值电压进行比较的第一比较器，并响应于此产生控制信号。 第二比较器将与升压转换器的输出相关联的第二电压与阈值电压进行比较，并响应于此产生第二控制信号。 驱动器电路产生第一开关晶体管驱动信号和第二开关晶体管驱动信号。 第一开关晶体管驱动信号用于驱动降压转换器的上栅极开关晶体管。 第二开关晶体管驱动信号可以被配置为第一操作模式以驱动降压转换器的下栅极开关晶体管，并且可以被配置为驱动升压转换器的开关晶体管的第二操作模式。 响应于控制信号和第二控制信号，控制逻辑启用/禁用至少一部分驱动器电路。

公开(公告)号：US20110255331A1

公开(公告)日：2011-10-20

申请号：US13158836

申请日：2011-06-13

Applicant: Jun Liu

Inventor： Jun Liu

IPC: G11C11/21

CPC classification number: G11C13/0004 ,  C07D213/81 ,  C07D401/06 ,  C07D401/12 ,  C07D401/14 ,  G11C5/025 ,  G11C5/063 ,  G11C13/0023 ,  G11C13/003 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/1021

Abstract: Memory devices and methods described are shown that provide improvements, including improved cell isolation for operations such as read and write. Further, methods and devices for addressing and accessing cells are shown that provide a simple and efficient way to manage devices with multiple cells associated with each access transistor. Examples of multiple cell devices include phase change memory devices with multiple cells associated with each access transistor.

Abstract translation: 显示了所描述的存储器件和方法，其提供了改进，包括改进的诸如读取和写入等操作的单元隔离。 此外，示出了用于寻址和访问单元的方法和设备，其提供用于管理具有与每个存取晶体管相关联的多个单元的器件的简单且有效的方式。 多个单元设备的示例包括具有与每个存取晶体管相关联的多个单元的相变存储器件。

公开(公告)号：US20110212247A1

公开(公告)日：2011-09-01

申请号：US12713479

申请日：2010-02-26

Applicant: Jun Liu ,  Scott McClinchey ,  Zenon Lisieczko

Inventor： Jun Liu ,  Scott McClinchey ,  Zenon Lisieczko

IPC: A23L1/10 ,  A01H5/00 ,  A01H1/02 ,  C12N15/82 ,  C12N15/31

CPC classification number: A01H5/10

Abstract: The invention relates to a novel canola line designated as SCV453784. The invention also relates to the seeds, the plants, and the plant parts of canola line SCV453784 as well as to methods for producing a canola plant produced by crossing canola line SCV453784 with itself or with another canola line. The invention also relates to methods for producing a canola plant containing in its genetic material one or more transgenes and to the transgenic canola plants and plant parts produced by those methods. The invention further relates to canola lines or breeding lines and plant parts derived from canola line SCV453784, to methods for producing other canola lines or plant parts derived from canola line SCV453784 and to the canola plants, varieties, and their parts derived from use of those methods. The invention additionally relates to hybrid canola seeds, plants, and plant parts produced by crossing the line SCV453784 with another canola line.

Abstract translation: 本发明涉及一种名为SCV453784的新型卡诺拉线。 本发明还涉及油菜籽系SCV453784的种子，植物和植物部分以及通过将卡诺拉油菜SCV453784自身或与另一种油菜线交叉生产的油菜植物的方法。 本发明还涉及在其遗传物质中含有一种或多种转基因和通过这些方法生产的转基因卡诺拉植物和植物部分产生卡诺拉植物的方法。 本发明进一步涉及卡诺拉线或育种系和源自卡诺拉线SCV453784的植物部分，以及用于生产其它卡诺拉线或衍生自卡诺拉线SCV453784的植物部分的方法以及来自使用那些的卡诺拉植物，品种及其部分 方法。 本发明另外涉及通过将SCV453784与另一个油菜线交叉产生的杂种卡诺拉种子，植物和植物部分。

公开(公告)号：US07961506B2

公开(公告)日：2011-06-14

申请号：US12026195

申请日：2008-02-05

Applicant: Jun Liu

Inventor： Jun Liu

IPC: G11C11/00

CPC classification number: G11C13/0004 ,  C07D213/81 ,  C07D401/06 ,  C07D401/12 ,  C07D401/14 ,  G11C5/025 ,  G11C5/063 ,  G11C13/0023 ,  G11C13/003 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/1021

Abstract: Memory devices and methods described are shown that provide improvements, including improved cell isolation for operations such as read and write. Further, methods and devices for addressing and accessing cells are shown that provide a simple and efficient way to manage devices with multiple cells associated with each access transistor. Examples of multiple cell devices include phase change memory devices with multiple cells associated with each access transistor.

Abstract translation: 显示了所描述的存储器件和方法，其提供了改进，包括改进的诸如读取和写入等操作的单元隔离。 此外，示出了用于寻址和访问单元的方法和设备，其提供用于管理具有与每个存取晶体管相关联的多个单元的器件的简单且有效的方式。 多个单元设备的示例包括具有与每个存取晶体管相关联的多个单元的相变存储器件。

公开(公告)号：US20110103129A1

公开(公告)日：2011-05-05

申请号：US12986717

申请日：2011-01-07

Applicant: Jun Liu

Inventor： Jun Liu

IPC: G11C11/00 ,  H01L21/02

CPC classification number: H01L21/8239 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/75 ,  H01L27/101 ,  H01L27/1052 ,  H01L27/24

Abstract: A variable-resistance material memory array includes a series of variable-resistance material memory cells. The series of variable-resistance material memory cells can be arranged in parallel with a corresponding series of control gates. A select gate can also be disposed in series with the variable-resistance material memory cells. Writing/reading/erasing to a given variable-resistance material memory cell can include turning off the corresponding control gate, while turning on all other control gates. Various devices can include such a variable-resistance material memory array.

Abstract translation: 可变电阻材料存储器阵列包括一系列可变电阻材料存储单元。 一系列可变电阻材料存储单元可以与相应的一系列控制栅极并联布置。 选择栅极也可以与可变电阻材料存储单元串联布置。 对给定的可变电阻材料存储单元的写入/读取/擦除可以包括在打开所有其它控制栅极的同时关闭对应的控制栅极。 各种装置可以包括这种可变电阻材料存储器阵列。