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公开(公告)号：US20240113059A1
公开(公告)日：2024-04-04
申请号：US18539143
申请日：2023-12-13
Inventor： Cyprian Emeka Uzoh , Jeremy Alfred Theil , Rajesh Katkar , Guilian Gao , Laura Wills Mirkarimi
IPC: H01L23/00
CPC classification number: H01L24/08 , H01L24/80 , H01L2224/08057 , H01L2224/08147 , H01L2224/80895 , H01L2224/80896
Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.
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公开(公告)号：US20240047344A1
公开(公告)日：2024-02-08
申请号：US18451366
申请日：2023-08-17
Inventor： Cyprian Emeka Uzoh , Gaius Gillman Fountain, Jr. , Jeremy Alfred Theil
IPC: H01L23/522 , H01L23/00 , H01L23/29 , H01L23/31
CPC classification number: H01L23/5226 , H01L24/20 , H01L23/298 , H01L23/3178
Abstract: Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers.
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公开(公告)号：US20230369136A1
公开(公告)日：2023-11-16
申请号：US17744383
申请日：2022-05-13
Inventor： Cyprian Emeka Uzoh , Oliver Zhao
IPC: H01L21/66 , H01L21/683 , H01L21/78
CPC classification number: H01L22/12 , H01L21/6836 , H01L21/78
Abstract: The disclosed technology relates to methods for forming and/or validating bonding surfaces of integrated device dies mounted on a dicing tape, and dicing tapes used thereof. In some embodiments, such a method for forming and validating a microelectronic assembly may include mounting a substrate to a dicing tape; singulating the substrate while the substrate is mounted to the dicing tape to form a plurality of dies; and validating a bonding surface of at least one die of the plurality of dies while the at least one die is mounted to the dicing tape. In some embodiments, such a dicing tape may include an anti-static adhesive layer arranged on an anti-static base film.
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公开(公告)号：US20230299029A1
公开(公告)日：2023-09-21
申请号：US18183828
申请日：2023-03-14
Inventor： Jeremy Alfred Theil , Thomas Workman , Cyprian Emeka Uzoh , Jesus Perez , Pawel Mrozek
IPC: H01L23/00
CPC classification number: H01L24/08 , H01L2224/0801 , H01L2224/08111 , H01L2224/08503
Abstract: An element and a bonded structure including the element are disclosed. The element can include a non-conductive region having a cavity extending at least partially through a thickness of the non-conductive region from the contact surface, and a contact feature formed in the cavity. The non-conductive region is configured to directly bond to a non-conductive region of a second element. The contact pad of the element is configured to directly bond to a contact pad of the second element. The contact pad can include a first conductive material and a second conductive material. The first conductive material can have a unit cell size greater than a unit cell size of the second conductive material. The first conductive material can be a metal alloying material. The first conductive material can be a metal silicide and the second conductive material can be a metal. A bonded conductive contact can include a conductive material and an alloying element, and an amount of the alloying element can vary through a thickness of the bonded conductive contact.
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公开(公告)号：US11742314B2
公开(公告)日：2023-08-29
申请号：US17208695
申请日：2021-03-22
Inventor： Cyprian Emeka Uzoh , Pawel Mrozek
CPC classification number: H01L24/80 , H01L24/08 , H01L2224/08145 , H01L2224/80011 , H01L2224/80013 , H01L2224/80031 , H01L2224/80895 , H01L2224/80896
Abstract: Reliable hybrid bonded apparatuses are provided. An example process cleans nanoparticles from at least the smooth oxide top layer of a surface to be hybrid bonded after the surface has already been activated for the hybrid bonding. Conventionally, such an operation is discouraged. However, the example cleaning processes described herein increase the electrical reliability of microelectronic devices. Extraneous metal nanoparticles can enable undesirable current and signal leakage from finely spaced traces, especially at higher voltages with ultra-fine trace pitches. In the example process, the extraneous nanoparticles may be both physically removed and/or dissolved without detriment to the activated bonding surface.
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Patent Agency Ranking
公开(公告)号：US20230268308A1
公开(公告)日：2023-08-24
申请号：US18067617
申请日：2022-12-16
Inventor： Gaius Gillman Fountain, JR. , Chandrasekhar Mandalapu , Cyprian Emeka Uzoh , Jeremy Alfred Theil
IPC: H01L23/00
CPC classification number: H01L24/27 , H01L24/30 , H01L24/32 , H01L24/83 , H01L24/29 , H01L24/05 , H01L24/06 , H01L24/03 , H01L2224/83905 , H01L2224/27462 , H01L2224/27616 , H01L2224/29147 , H01L2224/29155 , H01L2224/29186 , H01L2224/30505 , H01L2224/3003 , H01L2224/30131 , H01L2224/3015 , H01L2224/30517 , H01L2224/32145 , H01L2224/83895 , H01L2224/83896 , H01L2224/80986 , H01L2224/80035 , H01L2224/80935 , H01L2224/05547 , H01L2224/05181 , H01L2224/06155 , H01L2224/06152 , H01L2224/80357 , H01L2224/80896 , H01L2224/08145 , H01L2224/0603 , H01L24/80 , H01L2224/03616 , H01L2224/05166 , H01L2224/06131 , H01L2224/80895 , H01L2224/03462 , H01L2224/80948 , H01L2224/05647 , H01L2224/06136 , H01L2224/05155
Abstract: Representative implementations of techniques and methods include chemical mechanical polishing for hybrid bonding. The disclosed methods include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. Additionally, the conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer.
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公开(公告)号：US20230268300A1
公开(公告)日：2023-08-24
申请号：US18173690
申请日：2023-02-23
Inventor： Cyprian Emeka Uzoh , Rajesh Katkar , Thomas Workman , Gaius Gillman Fountain, Jr. , Guilian Gao , Jeremy Alfred Theil , Gabriel Z. Guevara , Kyong-Mo Bang , Laura Wills Mirkarimi
IPC: H01L23/00 , H01L25/16 , H01L25/065 , H01L23/498 , H01L23/48
CPC classification number: H01L24/08 , H01L25/16 , H01L25/0657 , H01L25/0655 , H01L25/0652 , H01L23/49838 , H01L23/481 , H01L24/80 , H01L2224/80895 , H01L2224/80896 , H01L2225/06524 , H01L2225/06527 , H01L2924/1011 , H01L2924/1815 , H01L2924/182 , H01L2224/08145 , H01L2224/08121 , H01L2224/08225
Abstract: A bonded structure can include a carrier including a first conductive contact and a second conductive contact, a first singulated element including a third conductive contact directly bonded to the first conductive contact without an adhesive, and a second singulated element including a fourth conductive contact directly bonded to the second conductive contact without an adhesive, wherein the first and second conductive contacts are spaced apart by a contact spacing of no more than 250 microns.
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公开(公告)号：US20230215836A1
公开(公告)日：2023-07-06
申请号：US18145607
申请日：2022-12-22
Inventor： Belgacem Haba , Rajesh Katkar , Guilian Gao , Cyprian Emeka Uzoh
IPC: H01L23/00
CPC classification number: H01L24/80 , H01L24/08 , H01L2224/08225 , H01L2224/80006 , H01L2224/80895 , H01L2224/80896
Abstract: A bonded structure with a package substrate comprising an inorganic, insulating first bonding layer and first conductive features at a surface thereof and an electronic component comprising an inorganic, insulating second bonding layer and second conductive features at a surface thereof wherein the first bonding layer and the second bonding layer are directly bonded to one another, and the first and second conductive features are directly bonded to one another.
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公开(公告)号：US20230197655A1
公开(公告)日：2023-06-22
申请号：US18068150
申请日：2022-12-19
Inventor： Jeremy Alfred Theil , Cyprian Emeka Uzoh , Guilian Gao
IPC: H01L23/00
CPC classification number: H01L24/08 , H01L24/05 , H01L2224/08145 , H01L2224/05583 , H01L2224/05582 , H01L2224/05647 , H01L2224/05686 , H01L2924/04941 , H01L2924/04953 , H01L2224/05681 , H01L2224/05693 , H01L2924/05432 , H01L2924/05042 , H01L2924/04642
Abstract: Methods for fabrication dielectric layers having conductive contact pads, and directly bonding the dielectric and conductive bonding surfaces of the dielectric layers. In some aspects, the method includes disposing a polish stop layer on dielectric bonding surfaces on top of a dielectric layer. A conductive layer is disposed on top of the polish stop layer and then polished to form conductive contact pads having polished conducting bonding surfaces. During the polishing process, the polish stop layer reduces rounding of dielectric edges and erosion of the dielectric bonding surfaces between closely spaced conductive bonding surfaces. The resulting polished dielectric and conductive bonding surfaces are directly bonded to dielectric and conductive bonding surfaces of another dielectric layer to form conductive interconnects.
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公开(公告)号：US20230187317A1
公开(公告)日：2023-06-15
申请号：US18064815
申请日：2022-12-12
Inventor： Cyprian Emeka Uzoh
IPC: H01L23/48 , H01L23/00 , H01L21/768 , H01L23/532
CPC classification number: H01L23/481 , H01L24/05 , H01L21/76898 , H01L21/76843 , H01L21/76807 , H01L23/53238 , H01L23/53257 , H01L2224/05647
Abstract: Disclosed is a semiconductor element including a semiconductor portion, a nonconductive layer on the semiconductor portion, an upper conductive layer formed of a first material and at least partially embedded in the nonconductive layer, a lower conductive layer below and electrically connected to the upper conductive layer, and a barrier layer disposed between the upper conductive layer and the lower conductive layer. The barrier layer is formed of a second material different from the first material, and the second material has an electrical resistivity less than 50×10−8 mΩ at 20° C. and a melting point greater than 1200° C.
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