公开(公告)号：US20240332227A1

公开(公告)日：2024-10-03

申请号：US18194544

申请日：2023-03-31

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC

Inventor： Cyprian Emeka Uzoh ,  Oliver Zhao

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/08 ,  H01L2224/03614 ,  H01L2224/0382 ,  H01L2224/03826 ,  H01L2224/03827 ,  H01L2224/03845 ,  H01L2224/05026 ,  H01L2224/05073 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/0517 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05638 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/08145 ,  H01L2924/01014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/0543

Abstract: A semiconductor element having an interconnect bonding layer with a contact pad and a plasma damage-free low-k dielectric material is disclosed. The contact pad connects an underlying conductive feature through an intervening via. A thin dielectric layer is disposed on and covering the entire sidewalls of the contact pad, the intervening via and the underlying conductive feature, and making an approximately right angle turn to extend along an interface between the low-k dielectric material and a first dielectric layer that at least partially bury the underlying contact feature.

公开(公告)号：US20230369136A1

公开(公告)日：2023-11-16

申请号：US17744383

申请日：2022-05-13

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Cyprian Emeka Uzoh ,  Oliver Zhao

IPC: H01L21/66 ,  H01L21/683 ,  H01L21/78

CPC classification number: H01L22/12 ,  H01L21/6836 ,  H01L21/78

Abstract: The disclosed technology relates to methods for forming and/or validating bonding surfaces of integrated device dies mounted on a dicing tape, and dicing tapes used thereof. In some embodiments, such a method for forming and validating a microelectronic assembly may include mounting a substrate to a dicing tape; singulating the substrate while the substrate is mounted to the dicing tape to form a plurality of dies; and validating a bonding surface of at least one die of the plurality of dies while the at least one die is mounted to the dicing tape. In some embodiments, such a dicing tape may include an anti-static adhesive layer arranged on an anti-static base film.

公开(公告)号：US20240217210A1

公开(公告)日：2024-07-04

申请号：US18148160

申请日：2022-12-29

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Oliver Zhao ,  Bongsub Lee ,  Cyprian Emeka Uzoh

IPC: B32B15/01 ,  B32B3/26 ,  B32B3/30 ,  B32B15/20

CPC classification number: B32B15/016 ,  B32B3/266 ,  B32B3/30 ,  B32B15/017 ,  B32B15/20 ,  B32B2250/02 ,  B32B2307/202 ,  B32B2307/206 ,  B32B2311/22 ,  B32B2311/24

Abstract: An element, bonded structure that includes the element, and methods forming the same are disclosed. A bonded structure can include a first element having a first nonconductive field region and a first conductive feature, and a second element having a second nonconductive field region and a second conductive feature. The second element is directly hybrid bonded to the first element such that the first and second nonconductive field regions are directly bonded to one another along a bond interface and the first and second conductive features are directly bonded to one another. The first conductive feature can include a perforated oxide layer. 1 at. % to 20 at. % of the first aluminum feature can be aluminum oxide.

公开(公告)号：US20250006674A1

公开(公告)日：2025-01-02

申请号：US18497585

申请日：2023-10-30

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Cyprian Emeka Uzoh ,  Oliver Zhao ,  Gabriel Z. Guevara ,  Dominik Suwito ,  Rajesh Katkar

IPC: H01L23/00

Abstract: A semiconductor element is provided with a micro-structured metal layer over conductive features of a hybrid bonding surface. The micro-structured metal layer comprises fine metal grain microstructure, such as nanograins. The micro-structured metal layer can be formed over the conductive features by providing a metal oxide and reducing the metal oxide to metal. The micro-structured metal layer can be formed selectively if the metal oxide is formed by oxidation. When directly bonded to another element, the micro-structured metal layer forming strong bonds at the bonding interface can substantially reduce annealing temperature.