Invention Application
- Patent Title: METHODS AND STRUCTURES FOR LOW TEMPERATURE HYBRID BONDING
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Application No.: US18497585Application Date: 2023-10-30
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Publication No.: US20250006674A1Publication Date: 2025-01-02
- Inventor: Cyprian Emeka Uzoh , Oliver Zhao , Gabriel Z. Guevara , Dominik Suwito , Rajesh Katkar
- Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Applicant Address: US CA San Jose
- Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Current Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Current Assignee Address: US CA San Jose
- Main IPC: H01L23/00
- IPC: H01L23/00

Abstract:
A semiconductor element is provided with a micro-structured metal layer over conductive features of a hybrid bonding surface. The micro-structured metal layer comprises fine metal grain microstructure, such as nanograins. The micro-structured metal layer can be formed over the conductive features by providing a metal oxide and reducing the metal oxide to metal. The micro-structured metal layer can be formed selectively if the metal oxide is formed by oxidation. When directly bonded to another element, the micro-structured metal layer forming strong bonds at the bonding interface can substantially reduce annealing temperature.
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