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    Nonvolatile semiconductor memory device and manufacturing method thereof
    61.
    发明申请
    Nonvolatile semiconductor memory device and manufacturing method thereof 失效
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20070291539A1

    公开(公告)日：2007-12-20

    申请号：US11699334

    申请日：2007-01-30

    Applicant: Atsuhiro Kinoshita ,  Riichiro Shirota ,  Hiroshi Watanabe ,  Kenichi Murooka ,  Junji Koga

    Inventor： Atsuhiro Kinoshita ,  Riichiro Shirota ,  Hiroshi Watanabe ,  Kenichi Murooka ,  Junji Koga

    IPC: G11C11/34 ,  H01L21/822

    CPC classification number: H01L27/115 ,  H01L27/11556 ,  H01L27/11568

    Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, plural semiconductor columns arranged in a matrix form on the substrate, plural first conductive areas zonally formed in a column direction on the substrate between the semiconductor columns and functioning as word lines, plural second conductive areas formed at tops of the semiconductor columns, respectively, plural bit lines connecting the second conductive areas in a row direction, plural channel areas respectively formed in the semiconductor columns between the first and second conductive areas and contacting the first and second conductive areas, plural third conductive areas continuously formed via first insulating films above the substrate and opposite to the channel areas in the column direction between the semiconductor columns and functioning as control gates, and plural charge accumulation areas respectively formed via second insulating films at upper portions of the channel areas at a position higher than the third conductive areas.

    Abstract translation: 非易失性半导体存储器件包括：半导体衬底，以矩阵形式布置在衬底上的多个半导体柱，在半导体柱之间的衬底上的列方向上分区形成的多个第一导电区域，并且用作字线，形成多个第二导电区域 在半导体柱的顶部分别分别连接在行方向上的第二导电区域的多个位线，分别形成在第一和第二导电区域之间的半导体柱中并与第一和第二导电区域接触的多个沟道区域，多个第三导电 通过基板上方的第一绝缘膜连续形成的区域，并且与半导体柱之间的列方向上的沟道区域相对，并且用作控制栅极，以及分别在沟道区域的上部经由第二绝缘膜形成的多个电荷累积区域 位置高 她比第三个导电区域。

    Nonvolatile semiconductor memory device
    62.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US07310270B2

    公开(公告)日：2007-12-18

    申请号：US11737154

    申请日：2007-04-19

    Applicant: Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

    Inventor： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

    IPC: G11C16/04

    CPC classification number: G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345 ,  G11C16/3454 ,  G11C16/3459 ,  G11C16/3463 ,  G11C2211/5621

    Abstract: A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of a selected memory cell, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

    Abstract translation: NAND单元单元包括串联连接的存储单元。 对所有存储单元进行擦除操作。 然后，将与擦除操作中施加的擦除电压极性相反的软编程电压施加到所有存储单元，从而将所有存储单元设置为过擦除状态。 此后，将20V的编程电压施加到所选择的存储单元的控制栅极，将0V施加到与所选择的存储单元相邻设置的两个存储单元的控制栅极，并且将11V施加到其余的控制栅极 记忆细胞 因此数据被编程到所选择的存储单元中。 根据要编程到所选择的存储单元中的数据来调整对所选存储单元施加编程电压的时间。 因此，可以将数据“0”正确地编程到所选择的存储单元中，可以从任何选择的存储单元高速读取多值数据。

    Nonvolatile semiconductor memory device having element isolating region of trench type
    67.
    发明申请
    Nonvolatile semiconductor memory device having element isolating region of trench type 有权
    具有沟槽型元件隔离区域的非易失性半导体存储器件

    公开(公告)号：US20060197226A1

    公开(公告)日：2006-09-07

    申请号：US11399657

    申请日：2006-04-07

    Applicant: Michiharu Matsui ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

    Inventor： Michiharu Matsui ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

    IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

    CPC classification number: H01L27/11526 ,  H01L21/76229 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11543 ,  H01L29/7887

    Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electrically connected to the first electrode layer via the open portion.

    Abstract translation: 公开是选择性栅极区域的半导体器件，包括半导体层，形成在半导体层上的第一绝缘膜，形成在第一绝缘层上的第一电极层，元件隔离区域，其包括形成为延伸穿过的元件隔离绝缘膜 所述第一电极层和所述第一绝缘膜到达所述半导体层的内部区域，所述元件隔离区域隔离元件区域并且与所述第一电极层自对准;第二绝缘膜，形成在所述第一电极层上， 元件隔离区域，暴露在第二绝缘膜中形成的第一电极层的表面的开口部分和形成在第二绝缘膜和第一电极层的暴露表面上的第二电极层，第二电极层是电气 经由开口部与第一电极层连接。

    Nonvolatile semiconductor memory and programming method for the same
    68.
    发明授权
    Nonvolatile semiconductor memory and programming method for the same 失效

    公开(公告)号：US07027329B2

    公开(公告)日：2006-04-11

    申请号：US10865937

    申请日：2004-06-14

    Applicant: Makoto Sakuma ,  Fumitaka Arai ,  Riichiro Shirota ,  Yasuhiko Matsunaga

    Inventor： Makoto Sakuma ,  Fumitaka Arai ,  Riichiro Shirota ,  Yasuhiko Matsunaga

    IPC: G11C16/04

    CPC classification number: G11C16/10

    Abstract: A semiconductor memory has a memory cell matrix including a plurality of first and second cell columns alternately arranged along a row-direction, each of cell columns is implemented by a plurality of memory cell transistors, and peripheral circuits configured to drive the memory cell matrix and to read information from the memory cell matrix. The peripheral circuit encompasses (a) a leading program circuit configured to write first data into memory cell transistors in the first cell columns, (b) a lagging program circuit configured to write second data into memory cell transistors in the second cell columns after the first data are written, and (c) a voltage controller configured to control variation of threshold voltages for the memory cell transistors of the first cell columns.

    Semiconductor memory device and electric device with the same
    70.
    发明申请
    Semiconductor memory device and electric device with the same 有权
    半导体存储器件和电器件相同

    公开(公告)号：US20050105335A1

    公开(公告)日：2005-05-19

    申请号：US10944910

    申请日：2004-09-21

    Applicant: Kikuko Sugimae ,  Takuya Futatsuyama ,  Riichiro Shirota ,  Masayuki Ichige

    Inventor： Kikuko Sugimae ,  Takuya Futatsuyama ,  Riichiro Shirota ,  Masayuki Ichige

    IPC: G11C16/06 ,  G11C5/02 ,  G11C5/06 ,  G11C8/10 ,  G11C8/12 ,  G11C16/00 ,  G11C16/04 ,  G11C16/08 ,  H01L21/8247 ,  H01L27/00 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

    CPC classification number: G11C8/12 ,  G11C8/10 ,  G11C16/08

    Abstract: A semiconductor memory device having: a cell array including bit lines, word lines and memory cells disposed at crossings thereof, plural memory cells being connected in series to constitute a NAND cell unit, plural blocks being arranged, each being constituted by plural NAND cell units arranged in the word line direction; and a row decoder configured to select a block, wherein the row decoder includes: transferring transistor arrays disposed in association with the blocks, in each of which transistors are arranged for transferring word line drive voltages; first decode portions disposed in association with the transferring transistor arrays, which are applied with boosted voltages to selectively drive the transferring transistor arrays; and second decode portions configured to select one of the blocks, each of which is disposed to be shared by adjacent two first decode portions.

    Abstract translation: 一种半导体存储器件，具有：包括位线，字线和位于其交叉处的存储单元的单元阵列，多个存储单元串联连接以构成NAND单元单元，多个块被布置，每个由多个NAND单元单元 排列在字线方向; 以及配置为选择块的行解码器，其中所述行解码器包括：传送与所述块相关联地布置的晶体管阵列，其中每个晶体管布置用于传送字线驱动电压; 与传输晶体管阵列相关联地设置的第一解码部分，其被施加升压电压以选择性地驱动传输晶体管阵列; 以及第二解码部分，被配置为选择所述块之一，每个块被布置为由相邻的两个第一解码部分共享。

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