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公开(公告)号：US07208933B2
公开(公告)日：2007-04-24
申请号：US11476722
申请日：2006-06-29
Applicant: Hiroshi Watanabe , Kazuya Matsuzawa , Riichiro Shirota
Inventor： Hiroshi Watanabe , Kazuya Matsuzawa , Riichiro Shirota
IPC: G01R19/00
CPC classification number: H01L29/7883 , G01R31/2642 , G06F9/3802 , G06F2221/2137 , G06K19/0723 , G06K19/073 , G06K19/07372 , G06Q20/341 , G07C9/00111 , G07C2009/00976 , G07F7/082 , G07F7/084 , G07F7/1008 , G11C16/14 , G11C16/349 , H01L21/28273 , H01L27/115 , H01L27/11558 , H01L29/42324 , H01L29/66825
Abstract: A time limit function utilization apparatus includes a first function block, a second function block, a signal line which connects the first and second function blocks and allows using a desired function that is generated by accessing the first and second function blocks with each other, and a semiconductor time switch interposed in or connected to the signal line, and disables or enables mutual access between the first and second function blocks upon the lapse of a predetermined time.
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公开(公告)号：US07248034B2
公开(公告)日：2007-07-24
申请号：US11476720
申请日：2006-06-29
Applicant: Hiroshi Watanabe , Kazuya Matsuzawa , Riichiro Shirota
Inventor： Hiroshi Watanabe , Kazuya Matsuzawa , Riichiro Shirota
IPC: G01R19/00
CPC classification number: H01L29/7883 , G01R31/2642 , G06F9/3802 , G06F2221/2137 , G06K19/0723 , G06K19/073 , G06K19/07372 , G06Q20/341 , G07C9/00111 , G07C2009/00976 , G07F7/082 , G07F7/084 , G07F7/1008 , G11C16/14 , G11C16/349 , H01L21/28273 , H01L27/115 , H01L27/11558 , H01L29/42324 , H01L29/66825
Abstract: A time limit function utilization apparatus includes a first function block, a second function block, a signal line which connects the first and second function blocks and allows using a desired function that is generated by accessing the first and second function blocks with each other, and a semiconductor time switch interposed in or connected to the signal line, and disables or enables mutual access between the first and second function blocks upon the lapse of a predetermined time.
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公开(公告)号：US20060152208A1
公开(公告)日：2006-07-13
申请号：US11353218
申请日：2006-02-14
Applicant: Hiroshi Watanabe , Kazuya Matsuzawa , Riichiro Shirota
Inventor： Hiroshi Watanabe , Kazuya Matsuzawa , Riichiro Shirota
IPC: G01R19/00
CPC classification number: H01L29/7883 , G01R31/2642 , G06F9/3802 , G06F2221/2137 , G06K19/0723 , G06K19/073 , G06K19/07372 , G06Q20/341 , G07C9/00111 , G07C2009/00976 , G07F7/082 , G07F7/084 , G07F7/1008 , G11C16/14 , G11C16/349 , H01L21/28273 , H01L27/115 , H01L27/11558 , H01L29/42324 , H01L29/66825
Abstract: A time limit function utilization apparatus includes a first function block, a second function block, a signal line which connects the first and second function blocks and allows using a desired function that is generated by accessing the first and second function blocks with each other, and a semiconductor time switch interposed in or connected to the signal line, and disables or enables mutual access between the first and second function blocks upon the lapse of a predetermined time.
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公开(公告)号：US07224157B2
公开(公告)日：2007-05-29
申请号：US11353218
申请日：2006-02-14
Applicant: Hiroshi Watanabe , Kazuya Matsuzawa , Riichiro Shirota
Inventor： Hiroshi Watanabe , Kazuya Matsuzawa , Riichiro Shirota
IPC: G01R19/00
CPC classification number: H01L29/7883 , G01R31/2642 , G06F9/3802 , G06F2221/2137 , G06K19/0723 , G06K19/073 , G06K19/07372 , G06Q20/341 , G07C9/00111 , G07C2009/00976 , G07F7/082 , G07F7/084 , G07F7/1008 , G11C16/14 , G11C16/349 , H01L21/28273 , H01L27/115 , H01L27/11558 , H01L29/42324 , H01L29/66825
Abstract: A time limit function utilization apparatus includes a first function block, a second function block, a signal line which connects the first and second function blocks and allows using a desired function that is generated by accessing the first and second function blocks with each other, and a semiconductor time switch interposed in or connected to the signal line, and disables or enables mutual access between the first and second function blocks upon the lapse of a predetermined time.
Abstract translation: 时间限制功能利用装置包括第一功能块，第二功能块，连接第一功能块和第二功能块的信号线，并且允许使用通过彼此访问第一和第二功能块而产生的期望功能，以及 插入或连接到信号线的半导体时间开关，并且在经过预定时间后禁用或使第一和第二功能块之间能够相互接近。
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公开(公告)号：US20060244435A1
公开(公告)日：2006-11-02
申请号：US11476722
申请日：2006-06-29
Applicant: Hiroshi Watanabe , Kazuya Matsuzawa , Riichiro Shirota
Inventor： Hiroshi Watanabe , Kazuya Matsuzawa , Riichiro Shirota
IPC: G01R19/00
CPC classification number: H01L29/7883 , G01R31/2642 , G06F9/3802 , G06F2221/2137 , G06K19/0723 , G06K19/073 , G06K19/07372 , G06Q20/341 , G07C9/00111 , G07C2009/00976 , G07F7/082 , G07F7/084 , G07F7/1008 , G11C16/14 , G11C16/349 , H01L21/28273 , H01L27/115 , H01L27/11558 , H01L29/42324 , H01L29/66825
Abstract: A time limit function utilization apparatus includes a first function block, a second function block, a signal line which connects the first and second function blocks and allows using a desired function that is generated by accessing the first and second function blocks with each other, and a semiconductor time switch interposed in or connected to the signal line, and disables or enables mutual access between the first and second function blocks upon the lapse of a predetermined time.
Abstract translation: 时间限制功能利用装置包括第一功能块，第二功能块，连接第一功能块和第二功能块的信号线，并且允许使用通过彼此访问第一和第二功能块而产生的期望功能，以及 插入或连接到信号线的半导体时间开关，并且在经过预定时间后禁用或使第一和第二功能块之间能够相互接近。
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公开(公告)号：US20060244434A1
公开(公告)日：2006-11-02
申请号：US11476720
申请日：2006-06-29
Applicant: Hiroshi Watanabe , Kazuya Matsuzawa , Riichiro Shirota
Inventor： Hiroshi Watanabe , Kazuya Matsuzawa , Riichiro Shirota
IPC: G01R19/00
CPC classification number: H01L29/7883 , G01R31/2642 , G06F9/3802 , G06F2221/2137 , G06K19/0723 , G06K19/073 , G06K19/07372 , G06Q20/341 , G07C9/00111 , G07C2009/00976 , G07F7/082 , G07F7/084 , G07F7/1008 , G11C16/14 , G11C16/349 , H01L21/28273 , H01L27/115 , H01L27/11558 , H01L29/42324 , H01L29/66825
Abstract: A time limit function utilization apparatus includes a first function block, a second function block, a signal line which connects the first and second function blocks and allows using a desired function that is generated by accessing the first and second function blocks with each other, and a semiconductor time switch interposed in or connected to the signal line, and disables or enables mutual access between the first and second function blocks upon the lapse of a predetermined time.
Abstract translation: 时间限制功能利用装置包括第一功能块，第二功能块，连接第一功能块和第二功能块的信号线，并且允许使用通过彼此访问第一和第二功能块而产生的期望功能，以及 插入或连接到信号线的半导体时间开关，并且在经过预定时间后禁用或使第一和第二功能块之间能够相互接近。
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公开(公告)号：US07075284B2
公开(公告)日：2006-07-11
申请号：US10612405
申请日：2003-07-03
Applicant: Hiroshi Watanabe , Kazuya Matsuzawa , Riichiro Shirota
Inventor： Hiroshi Watanabe , Kazuya Matsuzawa , Riichiro Shirota
IPC: G01R19/00
CPC classification number: H01L29/7883 , G01R31/2642 , G06F9/3802 , G06F2221/2137 , G06K19/0723 , G06K19/073 , G06K19/07372 , G06Q20/341 , G07C9/00111 , G07C2009/00976 , G07F7/082 , G07F7/084 , G07F7/1008 , G11C16/14 , G11C16/349 , H01L21/28273 , H01L27/115 , H01L27/11558 , H01L29/42324 , H01L29/66825
Abstract: A time limit function utilization apparatus includes a first function block, a second function block, a signal line which connects the first and second function blocks and allows using a desired function that is generated by accessing the first and second function blocks with each other, and a semiconductor time switch interposed in or connected to the signal line, and disables or enables mutual access between the first and second function blocks upon the lapse of a predetermined time.
Abstract translation: 时间限制功能利用装置包括第一功能块，第二功能块，连接第一功能块和第二功能块的信号线，并且允许使用通过彼此访问第一和第二功能块而产生的期望功能，以及 插入或连接到信号线的半导体时间开关，并且在经过预定时间后禁用或使第一和第二功能块之间能够相互接近。
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公开(公告)号：US20130003466A1
公开(公告)日：2013-01-03
申请号：US13533975
申请日：2012-06-27
Applicant: Riichiro Shirota , Hiroshi Watanabe
Inventor： Riichiro Shirota , Hiroshi Watanabe
IPC: H01L29/788 , G11C16/02
CPC classification number: G04F1/005 , H01L27/0928 , H01L27/11558 , H01L29/42324 , H01L29/42328 , H01L29/7881
Abstract: An application circuit and an operation method of a semiconductor device are provided. A leakage current among a control gate diffusion layer, a source diffusion layer and a drain is reduced by adjusting biases applied on a double well region, so as to reduce the product cost and improve the accuracy of a battery-less electronic timer that uses the semiconductor device.
Abstract translation: 提供了半导体器件的应用电路和操作方法。 控制栅极扩散层，源极扩散层和漏极之间的漏电流通过调整施加在双阱区域上的偏置来减小，从而降低产品成本并提高无电池电子定时器的精度， 半导体器件。
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公开(公告)号：US20170221916A1
公开(公告)日：2017-08-03
申请号：US15412128
申请日：2017-01-23
Applicant: Yukihiro Nagai , Riichiro Shirota , Hiroshi Watanabe , IMSolution Co., Ltd.
Inventor： Te-Chang Tseng , Yukihiro Nagai , Riichiro Shirota , Hiroshi Watanabe
IPC: H01L27/11568 , H01L29/423 , H01L29/51 , G11C16/04 , G11C16/14 , G11C16/26 , H01L29/16 , H01L27/11573 , G11C16/10
CPC classification number: H01L27/11568 , G11C5/063 , G11C16/0433 , G11C16/0466 , H01L27/11573 , H01L27/11582 , H01L28/00 , H01L29/16 , H01L29/42344 , H01L29/42348 , H01L29/4916 , H01L29/495 , H01L29/4966 , H01L29/513
Abstract: A cheap and high performance 1.5 transistor-type flash memory highly compatible to external of memory region is provided. The flash memory has sacrifice film formed on substrate. U-shaped groove is formed on sacrifice film, where multiple insulating film is laminated. Multiple insulating film includes silicon nitride film as charge storage layer. Low resistive material is disposed on multiple insulating film to form control gate. Select gate is formed on insulating film on side of control gate in self-aligned manner. Semiconductor regions opposite in conductivity to substrate on both sides of adjoining control gate and select gate to form source and drain, respectively. Thus, a 1.5 transistor-type flash memory is formed with adjoining control gate and select gate between source and drain. In MOS-type transistor with control gate, threshold voltage is changeable according to injection/emission of charge to silicon nitride as charge storage layer, and thus work as non-volatile memory.
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10.发明申请
公开(公告)号：US20070291539A1
公开(公告)日：2007-12-20
申请号：US11699334
申请日：2007-01-30
Applicant: Atsuhiro Kinoshita , Riichiro Shirota , Hiroshi Watanabe , Kenichi Murooka , Junji Koga
Inventor： Atsuhiro Kinoshita , Riichiro Shirota , Hiroshi Watanabe , Kenichi Murooka , Junji Koga
IPC: G11C11/34 , H01L21/822
CPC classification number: H01L27/115 , H01L27/11556 , H01L27/11568
Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, plural semiconductor columns arranged in a matrix form on the substrate, plural first conductive areas zonally formed in a column direction on the substrate between the semiconductor columns and functioning as word lines, plural second conductive areas formed at tops of the semiconductor columns, respectively, plural bit lines connecting the second conductive areas in a row direction, plural channel areas respectively formed in the semiconductor columns between the first and second conductive areas and contacting the first and second conductive areas, plural third conductive areas continuously formed via first insulating films above the substrate and opposite to the channel areas in the column direction between the semiconductor columns and functioning as control gates, and plural charge accumulation areas respectively formed via second insulating films at upper portions of the channel areas at a position higher than the third conductive areas.
Abstract translation: 非易失性半导体存储器件包括：半导体衬底，以矩阵形式布置在衬底上的多个半导体柱，在半导体柱之间的衬底上的列方向上分区形成的多个第一导电区域，并且用作字线，形成多个第二导电区域 在半导体柱的顶部分别分别连接在行方向上的第二导电区域的多个位线，分别形成在第一和第二导电区域之间的半导体柱中并与第一和第二导电区域接触的多个沟道区域，多个第三导电 通过基板上方的第一绝缘膜连续形成的区域，并且与半导体柱之间的列方向上的沟道区域相对，并且用作控制栅极，以及分别在沟道区域的上部经由第二绝缘膜形成的多个电荷累积区域 位置高 她比第三个导电区域。
