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    Method Forming Gate Stacks Adopting Thin Silicon Cap
    51.
    发明公开
    Method Forming Gate Stacks Adopting Thin Silicon Cap 审中-公开

    公开(公告)号：US20230238241A1

    公开(公告)日：2023-07-27

    申请号：US17663050

    申请日：2022-05-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jyun-Yi Wu ,  Chung-Yi Su ,  Tsung-Da Lin ,  Chi On Chui

    IPC: H01L21/28 ,  H01L29/66

    CPC classification number: H01L21/28185 ,  H01L29/66545 ,  H01L29/66795

    Abstract: A method includes forming a dummy gate stack on a semiconductor region, forming gate spacers on sidewalls of the dummy gate stack, removing the dummy gate stack to form a recess between the gate spacers, and forming a silicon oxide layer on the semiconductor region. The silicon oxide layer extends into the recess. A high-k dielectric layer is deposited over the silicon oxide layer, and a silicon layer is deposited over the high-k dielectric layer. The silicon layer extends into the recess. The high-k dielectric layer and the silicon layer are in-situ deposited in a same vacuum environment. The method further includes performing an annealing process on the silicon layer and the high-k dielectric layer, removing the silicon layer, and forming a gate electrode over the high-k dielectric layer. The gate electrode fills the recess.

    Non-Conformal Gate Oxide Formation on FinFET
    56.
    发明申请
    Non-Conformal Gate Oxide Formation on FinFET 有权

    公开(公告)号：US20230126442A1

    公开(公告)日：2023-04-27

    申请号：US17662532

    申请日：2022-05-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsung-Ju Chen ,  Shu-Han Chen ,  Chun-Heng Chen ,  Chi On Chui

    IPC: H01L29/66

    Abstract: A method includes forming a dummy gate oxide on a wafer, and the dummy gate oxide is formed on a sidewall and a top surface of a protruding semiconductor fin in the wafer. The formation of the dummy gate oxide may include a Plasma Enhanced Chemical Vapor Deposition (PECVD) process in a deposition chamber, and the PECVD process includes applying a Radio Frequency (RF) power to a conductive plate below the wafer. The method further includes forming a dummy gate electrode over the dummy gate oxide, removing the dummy gate electrode and the dummy gate oxide to form a trench between opposing gate spacers, and forming a replacement gate in the trench.

    GATE STRUCTURES IN TRANSISTORS AND METHOD OF FORMING SAME
    57.
    发明申请
    GATE STRUCTURES IN TRANSISTORS AND METHOD OF FORMING SAME 有权

    公开(公告)号：US20230066477A1

    公开(公告)日：2023-03-02

    申请号：US17462233

    申请日：2021-08-31

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

    IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/51 ,  H01L29/40

    Abstract: Embodiments include a device and method of forming a device, such as a nano-FET transistor, including a first nanostructure. A gate dielectric is formed around the first nanostructure. A gate electrode is formed over the gate dielectric, and the gate electrode includes a first work function metal. In the gate electrode, a first metal residue is formed at an interface between the gate dielectric and the first work function metal as a result of a treatment process performed prior to forming the first work function metal. The first metal residue has a metal element that is different than a metal element of the first work function metal.

    NFET with Aluminum-Free Work-Function Layer and Method Forming Same
    59.
    发明申请
    NFET with Aluminum-Free Work-Function Layer and Method Forming Same 有权

    公开(公告)号：US20230020099A1

    公开(公告)日：2023-01-19

    申请号：US17648152

    申请日：2022-01-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui ,  Chun-I Wu ,  Huang-Lin Chao

    IPC: H01L29/40 ,  H01L29/66 ,  H01L29/49 ,  H01L21/285 ,  H01L21/28

    Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, depositing a metal-containing layer over the gate dielectric layer, and depositing a silicon-containing layer on the metal-containing layer. The metal-containing layer and the silicon-containing layer in combination act as a work-function layer. A planarization process is performed to remove excess portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer, with remaining portions of the silicon-containing layer, the silicon-containing layer, and the gate dielectric layer forming a gate stack.

    VERTICAL DRAM STRUCTURE AND METHOD
    60.
    发明申请
    VERTICAL DRAM STRUCTURE AND METHOD 有权

    公开(公告)号：US20220406784A1

    公开(公告)日：2022-12-22

    申请号：US17668770

    申请日：2022-02-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chia-Ta Yu ,  Bo-Feng Young ,  Hung Wei Li ,  Sai-Hooi Yeong ,  Chi On Chui

    IPC: H01L27/108 ,  H01L29/10

    Abstract: Embodiments of the present disclosure provide a side-channel dynamic random access memory (DRAM) cell and cell array that utilizes a vertical design with side channel transistors. A dielectric layer disposed over a substrate. A gate electrode is embedded in the dielectric layer. A channel layer wraps the gate electrode and a conductive structure is adjacent to the channel layer, with the channel layer interposed between the gate electrode and the conductive structure. The semiconductor structure also includes a dielectric structure disposed over the conductive structure and the gate electrode, the channel layer extending up through the dielectric structure.

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