公开(公告)号：US20240385507A1

公开(公告)日：2024-11-21

申请号：US18787490

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ta Lu ,  Chih-Chiang Tu ,  Cheng-Ming Lin ,  Ching-Yueh Chen ,  Wei-Chung Hu ,  Ting-Chang Hsu ,  Yu-Tung Chen

IPC: G03F1/24 ,  G03F1/36 ,  G03F1/38 ,  G03F1/54 ,  G03F1/64 ,  G03F7/20

Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.

公开(公告)号：US12107134B2

公开(公告)日：2024-10-01

申请号：US18065442

申请日：2022-12-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ming Lin ,  Peng-Soon Lim ,  Zi-Wei Fang

IPC: H01L29/417 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/823437 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/823821

Abstract: A device includes a semiconductor channel region and a gate structure. The semiconductor channel region is on a substrate. The gate structure is over the semiconductor channel region and comprises a gate dielectric layer, a first gate conductor layer, and a second gate conductor layer. The first gate conductor layer is over the gate dielectric layer. The first gate conductor layer includes oxygen. The second gate conductor layer is over the first gate conductor layer.

公开(公告)号：US11282933B2

公开(公告)日：2022-03-22

申请号：US16031859

申请日：2018-07-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Peng-Soon Lim ,  Zi-Wei Fang ,  Cheng-Ming Lin

IPC: H01L29/78 ,  H01L29/423 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L21/28 ,  H01L29/10 ,  H01L29/417

Abstract: A semiconductor device includes a semiconductor substrate having a channel region. A gate dielectric layer is over the channel region of the semiconductor substrate. A work function metal layer is over the gate dielectric layer. The work function metal layer has a bottom portion, an upper portion, and a work function material. The bottom portion is between the gate dielectric layer and the upper portion. The bottom portion has a first concentration of the work function material, the upper portion has a second concentration of the work function material, and the first concentration is higher than the second concentration. A gate electrode is over the upper portion of the work function metal layer.

公开(公告)号：US20200335599A1

公开(公告)日：2020-10-22

申请号：US16946736

申请日：2020-07-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Kai Tak Lam ,  Sai-Hooi Yeong ,  Chi On Chui ,  Ziwei Fang

IPC: H01L29/51 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L21/768

Abstract: A semiconductor structure that includes a semiconductor fin disposed over a substrate, S/D features disposed over the semiconductor fin, and a metal gate stack interposed between the S/D features. The metal gate stack includes a gate dielectric layer disposed over the semiconductor fin, a capping layer disposed over the gate dielectric layer, and a gate electrode disposed over the capping layer, where the gate dielectric layer includes hafnium oxide with hafnium atoms and oxygen atoms arranged in a Pca21 space group.

公开(公告)号：US10101651B1

公开(公告)日：2018-10-16

申请号：US15486305

申请日：2017-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： SHao-Chi Wei ,  Cheng-Ming Lin ,  Sheng-Chang Hsu ,  Yu-Hsin Hsu ,  Hao-Ming Chang

IPC: G03B27/58 ,  G03F1/64 ,  G03F1/22 ,  G03F1/60 ,  G03F7/20

Abstract: A photo mask assembly including a photo mask, a first adhesive layer adhered with the photo mask, a pellicle frame and a pellicle is provided. The pellicle frame includes a plurality of recesses for accommodating the first adhesive layer. The pellicle frame is adhered with the photo mask through the first adhesive layer accommodated in the plurality of recesses. The pellicle is disposed on the pellicle frame. The pellicle frame is between the pellicle and the first adhesive layer. An optical apparatus including the above-mentioned photo mask assembly is also provided.

公开(公告)号：US11901450B2

公开(公告)日：2024-02-13

申请号：US17362317

申请日：2021-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Ziwei Fang ,  Bo-Feng Young ,  Chi On Chui ,  Chih-Yu Chang ,  Huang-Lin Chao

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L29/78391 ,  H01L21/0234 ,  H01L21/02181 ,  H01L21/02356 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/66795 ,  H01L29/7851

Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.

公开(公告)号：US11855164B2

公开(公告)日：2023-12-26

申请号：US17327584

申请日：2021-05-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ming Lin ,  Peng-Soon Lim ,  Zi-Wei Fang

IPC: H01L29/417 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/41791 ,  H01L21/823437 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/823821

Abstract: A semiconductor device includes a substrate, a semiconductor fin extending from the substrate, a gate dielectric layer over the semiconductor fin, a metal nitride layer comprising a first portion over the gate dielectric layer and a second portion over the first portion, and a fill layer over the metal nitride layer. The second portion has an aluminum concentration greater than an aluminum concentration of the first portion.

公开(公告)号：US20210296503A1

公开(公告)日：2021-09-23

申请号：US17339615

申请日：2021-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Chi On Chui ,  Ziwei Fang ,  Huang-Lin Chao

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66

Abstract: A semiconductor structure includes gate spacers disposed over a semiconductor layer, a hafnium-containing dielectric layer, where a first portion of the hafnium-containing dielectric layer having a first thickness is disposed over the semiconductor layer and a second portion of the hafnium-containing dielectric layer having a second thickness is disposed along sidewalls of the gate spacers, and where the first thickness is greater than the second thickness, and a metal gate electrode disposed over the hafnium-containing dielectric layer and between the gate spacers.

公开(公告)号：US11069807B2

公开(公告)日：2021-07-20

申请号：US16515898

申请日：2019-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Ziwei Fang ,  Bo-Feng Young ,  Chi On Chui ,  Chih-Yu Chang ,  Huang-Lin Chao

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/28

Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.

公开(公告)号：US10739671B2

公开(公告)日：2020-08-11

申请号：US15905543

申请日：2018-02-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh Tien ,  Cheng-Hsuen Chiang ,  Chih-Ming Chen ,  Cheng-Ming Lin ,  Yen-Wei Huang ,  Hao-Ming Chang ,  Kuo Chin Lin ,  Kuan-Shien Lee

IPC: G03F1/32 ,  G03F1/38

Abstract: In a method of manufacturing a photo mask, a resist layer is formed over a mask blank, which includes a mask substrate, a phase shift layer disposed on the mask substrate and a light blocking layer disposed on the phase shift layer. A resist pattern is formed by using a lithographic operation. The light blocking layer is patterned by using the resist pattern as an etching mask. The phase shift layer is patterned by using the patterned light blocking layer as an etching mask. A border region of the mask substrate is covered with an etching hard cover, while a pattern region of the mask substrate is opened. The patterned light blocking layer in the pattern region is patterned through the opening of the etching hard cover. A photo-etching operation is performed on the pattern region to remove residues of the light blocking layer.