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公开(公告)号：US12124163B2
公开(公告)日：2024-10-22
申请号：US18359954
申请日：2023-07-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chi-Ta Lu , Chih-Chiang Tu , Cheng-Ming Lin , Ching-Yueh Chen , Wei-Chung Hu , Ting-Chang Hsu , Yu-Tung Chen
Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
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公开(公告)号：US11860530B2
公开(公告)日：2024-01-02
申请号：US17809979
申请日：2022-06-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chi-Ta Lu , Chih-Chiang Tu , Cheng-Ming Lin , Ching-Yueh Chen , Wei-Chung Hu , Ting-Chang Hsu , Yu-Tung Chen
Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
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公开(公告)号：US20180284595A1
公开(公告)日：2018-10-04
申请号：US15475137
申请日：2017-03-31
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ching-Hung Lai , Chih-Chung Huang , Chih-Chiang Tu , Chung-Hung Lin , Chi-Ming Tsai , Ming-Ho Tsai
CPC classification number: G03F1/22 , G03F1/36 , G03F7/7015 , G03F7/70441
Abstract: A mask includes a transparent substrate, a first pattern, a second pattern, and a sub-resolution auxiliary feature. The first pattern and the second pattern are over the transparent substrate. The first pattern has an area of 0.16 μm2 to 60000 μm2. The second pattern has an area of 0.16 μm2 to 60000 μm2. The sub-resolution auxiliary feature is over the transparent substrate and connects the first pattern and the second pattern.
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公开(公告)号：US10276426B2
公开(公告)日：2019-04-30
申请号：US15204761
申请日：2016-07-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Chiang Tu , Chun-Lang Chen
IPC: H01L21/687 , H01L21/3065 , H01L21/67 , H01J37/32
Abstract: A spin dry etching process includes loading an object into a dry etching system. A dry etching process is performed to the object, and the object is spun while the dry etching process is being performed. The spin dry etching process is performed using a semiconductor fabrication system. The semiconductor fabrication system includes a dry etching chamber in which a dry etching process is performed. A holder apparatus has a horizontally-facing slot that is configured for horizontal insertion of an etchable object therein. The etchable object includes either a photomask or a wafer. A controller is communicatively coupled to the holder apparatus and configured to spin the holder apparatus in a clockwise or counterclockwise direction while the dry etching process is being performed. An insertion of the etchable object into the horizontally-facing slot of the holder apparatus restricts a movement of the object as the dry etching process is performed.
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公开(公告)号：US20180059534A1
公开(公告)日：2018-03-01
申请号：US15356204
申请日：2016-11-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Chiang Tu , Chun-Lang Chen , Chue San Yoo , Jong-Yuh Chang , Chia-Shiung Tsai , Ping-Yin Liu , Hsin-Chang Lee , Chih-Cheng Lin , Yun-Yue Lin
IPC: G03F1/62 , H01L21/033
CPC classification number: G03F1/62 , C23C14/16 , C23C14/165 , C23C14/18 , C23C16/01 , C23C16/26 , C23C16/56 , C23C28/32 , G03F1/64 , H01L21/0332 , H01L21/0335 , H01L21/0337
Abstract: A method includes depositing a first material layer over a first substrate; and depositing a graphene layer over the first material layer. The method further includes depositing an amorphous silicon layer over the graphene layer and bonding the amorphous silicon layer to a second substrate, thereby forming an assembly. The method further includes annealing the assembly, thereby converting the amorphous silicon layer to a silicon oxide layer. The method further includes removing the first substrate from the assembly and removing the first material layer from the assembly, thereby exposing the graphene layer.
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Patent Agency Ranking
公开(公告)号：US09017903B2
公开(公告)日：2015-04-28
申请号：US13947180
申请日：2013-07-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Chiang Tu , Chun-Lang Chen , Jong-Yuh Chang , Chien-Chih Chen , Chen-Shao Hsu
Abstract: Some embodiments of the present disclosure relate to a method of patterning a workpiece with a mask, wherein a scale factor between a geometry of the mask and a corresponding target shape of the mask is determined. The scale factor results from thermal expansion of the mask and geometry due to heating of the mask during exposure to radiation by an electron beam (e-beam) in the mask manufacturing process. A number of radiation pulses necessary to dispose the geometry on the mask is determined. A scale factor for the mask is then determined from the number of pulses. The target shape is then generated on the mask by re-scaling the geometry according to the scale factor prior to mask manufacturing. This method compensates for thermal deformation due to e-beam heating to improve OVL variability in advanced technology nodes.
Abstract translation: 本公开的一些实施例涉及用掩模图案化工件的方法，其中确定掩模的几何形状与掩模的对应目标形状之间的比例因子。 缩放因子是由掩模的热膨胀和几何形状引起的，这是由于在掩模制造过程中通过电子束（电子束）暴露于辐射期间掩模的加热。 确定将几何形状设置在掩模上所需的许多辐射脉冲。 然后根据脉冲数确定掩模的比例因子。 然后通过在掩模制造之前根据比例因子重新缩放几何形状，在掩模上生成目标形状。 该方法补偿了电子束加热引起的热变形，提高了先进技术节点的OVL变化。
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公开(公告)号：US20150024306A1
公开(公告)日：2015-01-22
申请号：US13947180
申请日：2013-07-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Chiang Tu , Chun-Lang Chen , Jong-Yuh Chang , Chien-Chih Chen , Chen-Shao Hsu
IPC: G03F1/82
Abstract: Some embodiments of the present disclosure relate to a method of patterning a workpiece with a mask, wherein a scale factor between a geometry of the mask and a corresponding target shape of the mask is determined. The scale factor results from thermal expansion of the mask and geometry due to heating of the mask during exposure to radiation by an electron beam (e-beam) in the mask manufacturing process. A number of radiation pulses necessary to dispose the geometry on the mask is determined. A scale factor for the mask is then determined from the number of pulses. The target shape is then generated on the mask by re-scaling the geometry according to the scale factor prior to mask manufacturing. This method compensates for thermal deformation due to e-beam heating to improve OVL variability in advanced technology nodes.
Abstract translation: 本公开的一些实施例涉及用掩模图案化工件的方法，其中确定掩模的几何形状与掩模的对应目标形状之间的比例因子。 缩放因子是由掩模的热膨胀和几何形状引起的，这是由于在掩模制造过程中通过电子束（电子束）暴露于辐射期间掩模的加热。 确定将几何形状设置在掩模上所需的许多辐射脉冲。 然后根据脉冲数确定掩模的比例因子。 然后通过在掩模制造之前根据比例因子重新缩放几何形状，在掩模上生成目标形状。 该方法补偿了电子束加热引起的热变形，提高了先进技术节点的OVL变化。
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公开(公告)号：US20230367197A1
公开(公告)日：2023-11-16
申请号：US18359954
申请日：2023-07-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chi-Ta Lu , Chih-Chiang Tu , Cheng-Ming Lin , Ching-Yueh Chen , Wei-Chung Hu , Ting-Chang Hsu , Yu-Tung Chen
Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
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公开(公告)号：US20210333705A1
公开(公告)日：2021-10-28
申请号：US16860080
申请日：2020-04-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Che-Yuan Chang , Chih-Chiang Tu , Ming-Ho Tsai , Ching-Hung Lai
Abstract: A photomask includes a transparent substrate and a shielding pattern disposed on the transparent substrate. The shielding pattern includes shielding island structures. The shielding island structures are separated from and spaced apart from one another by dividing lanes. The dividing lanes expose the underlying transparent substrate. The photomask is configured for a light of a wavelength, and the dividing lanes reduce or hinder a transmission of the light of the wavelength.
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公开(公告)号：US11099476B2
公开(公告)日：2021-08-24
申请号：US16879889
申请日：2020-05-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Chiang Tu , Chun-Lang Chen
Abstract: Some embodiments pertain to a photomask for mask patterning. The photomask includes a phase shift layer overlying a transparent layer, a first shielding layer overlying the phase shift layer, and a second shielding layer overlying the first shielding layer. The first shielding layer has a first optical density, and the second shielding layer has a second optical density. The second optical density is less than the first optical density.
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