公开(公告)号：US20160225764A1

公开(公告)日：2016-08-04

申请号：US15086433

申请日：2016-03-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/49 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/51

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/31055 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6681

Abstract: A semiconductor device includes first and second Fin FET transistors and a separation plug made of an insulating material and disposed between the first and second Fin FET transistors. The first Fin FET transistor includes a first fin structure extending in a first direction, a first gate dielectric formed over the first fin structure and a first gate electrode formed over the first gate dielectric and extending a second direction perpendicular to the first direction. The second Fin FET transistor includes a second fin structure, a second gate dielectric formed over the second fin structure and a second gate electrode formed over the first gate dielectric and extending the second direction. In across section along the second direction and across the first gate electrode, the second gate electrode and the separation plug, the separation plug has a tapered shape having atop size smaller than a bottom size.

Abstract translation: 半导体器件包括第一和第二Fin FET晶体管和由绝缘材料制成并分布在第一和第二Fin FET晶体管之间的分离插头。 第一Fin FET晶体管包括在第一方向上延伸的第一鳍结构，形成在第一鳍结构上的第一栅极电介质和形成在第一栅极电介质上并且垂直于第一方向延伸的第二方向的第一栅电极。 第二鳍FET晶体管包括第二鳍结构，形成在第二鳍结构上的第二栅极电介质和形成在第一栅极电介质上并延伸第二方向的第二栅电极。 在沿着第二方向跨过第一栅电极，第二栅电极和分离塞的横截面中，分离塞具有顶部尺寸小于底部尺寸的锥形形状。

公开(公告)号：US20160148935A1

公开(公告)日：2016-05-26

申请号：US14554682

申请日：2014-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Yin CHEN ,  Tung-Wen CHENG ,  Che-Cheng CHANG ,  Chun-Lung NI ,  Jr-Jung LIN ,  Chih-Han LIN

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/51 ,  H01L21/033 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/311 ,  H01L27/088 ,  H01L29/49

CPC classification number: H01L21/0338 ,  H01L21/0206 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure is provided. The FinFET device structure includes a substrate and a first fin structure and a second fin structure extending above the substrate. The FinFET device structure also includes a first transistor formed on the first fin structure and a second transistor formed on the second fin structure. The FinFET device structure further includes an inter-layer dielectric (ILD) structure formed in an end-to-end gap between the first transistor and the second transistor, and the end-to-end gap has a width in a range from about 20 nm to about 40 nm.

Abstract translation: 提供了一种用于形成FinFET器件结构的鳍式场效应晶体管（FinFET）器件结构和方法。 FinFET器件结构包括衬底和在衬底上方延伸的第一鳍结构和第二鳍结构。 FinFET器件结构还包括形成在第一鳍结构上的第一晶体管和形成在第二鳍结构上的第二晶体管。 FinFET器件结构还包括形成在第一晶体管和第二晶体管之间的端到端间隙中的层间电介质（ILD）结构，并且端对端间隙具有在约20° nm至约40nm。

公开(公告)号：US20240178300A1

公开(公告)日：2024-05-30

申请号：US18432694

申请日：2024-02-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin CHEN ,  Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L21/02 ,  H01L21/027 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321 ,  H01L21/762

CPC classification number: H01L29/4991 ,  H01L21/28088 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L21/0206 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/76224 ,  H01L29/4966

Abstract: A device includes a semiconductor fin semiconductor fin extending from a substrate, a gate structure extending across the semiconductor fin, and a multilayer gate spacer on a sidewall of the gate structure. The multilayer gate spacer includes an inner spacer layer, an outer spacer layer, and a dielectric structure. The inner spacer layer has a vertical portion extending along the sidewall of the gate structure, and a lateral portion laterally extending from the vertical portion in a direction away from the gate structure. The outer spacer layer is spaced apart from the vertical portion of the inner spacer layer by an air gap. The dielectric structure spaces apart a bottom end of the outer spacer layer from the lateral portion of the inner spacer layer.

公开(公告)号：US20230369059A1

公开(公告)日：2023-11-16

申请号：US18361464

申请日：2023-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin CHEN ,  Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L23/31

CPC classification number: H01L21/3081 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/785 ,  H01L23/3157

Abstract: A semiconductor device includes a semiconductor fin extending from a substrate, and a gate structure extending across the semiconductor fin. From a plan view, the semiconductor fin includes a first sidewall, a second sidewall opposing the first sidewall, an end surface extending along a different direction than the first sidewall and the second sidewall, and a first corner portion connecting the first sidewall and the end surface. The first corner portion is more rounded than the first sidewall and the end surface.

公开(公告)号：US20210351065A1

公开(公告)日：2021-11-11

申请号：US17383299

申请日：2021-07-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/485

Abstract: An interconnection structure comprises a first metal structure, a first dielectric layer, a second dielectric layer, a second metal structure, a first protective layer, and a second protective layer. The first dielectric layer is over the first metal structure. The second dielectric layer is over the first dielectric layer. The second metal structure has an upper portion extending through the second dielectric layer, and a lower portion extending through the first dielectric layer. The upper portion has a width greater than a width of the lower portion. The first protective layer spaces the first dielectric layer apart from the lower portion of the second metal structure. The second protective layer spaces the second dielectric layer apart from the upper portion of the second metal structure, and has a top width greater than a top width of the first protective layer.

公开(公告)号：US20210066501A1

公开(公告)日：2021-03-04

申请号：US17098046

申请日：2020-11-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

Abstract: A device includes a substrate, a shallow trench isolation (STI) structure, an isolation structure, and a gate stack. The substrate has a semiconductor fin. The shallow trench isolation (STI) structure is over the substrate and laterally surrounding the semiconductor fin. The isolation structure is disposed on a top surface of the STI structure. The gate stack crosses the semiconductor fin, over the STI structure, and in contact with a sidewall the isolation structure, in which the gate stack includes a high-k dielectric layer extending from a sidewall of the semiconductor fin to the top surface of the STI structure and terminating prior to reaching the sidewall of the isolation structure, and in which the high-k dielectric layer is in contact with the top surface of the STI structure.

公开(公告)号：US20200066530A1

公开(公告)日：2020-02-27

申请号：US16666218

申请日：2019-10-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Po-Chi WU ,  Chih-Han LIN ,  Horng-Huei TSENG

IPC: H01L21/225 ,  H01L29/36 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12

Abstract: A semiconductor device includes a substrate, a FinFET, and an insulating structure. The FinFET includes a fin, a gate electrode, and a gate dielectric layer. The fin is over the substrate. The gate electrode is over the fin. The gate dielectric layer is between the gate electrode and the fin. The insulating structure is over the substrate, adjacent the fin, and has a top surface lower than a top surface of the fin. The top surface of the insulating structure has opposite first and second edge portions and an intermediate portion between the first and second edge portions. The first edge portion of the top surface of the insulating structure is lower than the intermediate portion of the top surface of the insulating structure.

公开(公告)号：US20190115253A1

公开(公告)日：2019-04-18

申请号：US16206768

申请日：2018-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L21/768 ,  H01L23/528

Abstract: A method of forming an interconnection structure includes following steps. A dielectric structure is deposited over a non-insulator structure. The dielectric structure is etched to form a via opening. A mask layer is formed over the dielectric structure. The mask layer is patterned. An anti-adhesion layer is deposited on a sidewall of the via opening after patterning the mask layer. The dielectric structure is etched to form a trench opening, wherein the patterned mask layer is used as an etch mask during forming the trench opening. A conductive structure is formed in the via opening and the trench opening.

公开(公告)号：US20180182857A1

公开(公告)日：2018-06-28

申请号：US15901343

申请日：2018-02-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L27/092

Abstract: A Fin FET semiconductor device includes a fin structure extending in a first direction and extending from an isolation insulating layer. The Fin FET device also includes a gate stack including a gate electrode layer, a gate dielectric layer, side wall insulating layers disposed at both sides of the gate electrode layer, and interlayer dielectric layers disposed at both sides of the side wall insulating layers. The gate stack is disposed over the isolation insulating layer, covers a portion of the fin structure, and extends in a second direction perpendicular to the first direction. A recess is formed in an upper surface of the isolation insulating layer not covered by the side wall insulating layers and the interlayer dielectric layers. At least part of the gate electrode layer and the gate dielectric layer fill the recess.

公开(公告)号：US20180175030A1

公开(公告)日：2018-06-21

申请号：US15894825

申请日：2018-02-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN ,  Horng-Huei TSENG

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/28114 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823456 ,  H01L27/088 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate, a core device disposed above the substrate, and an input/output (I/O) device disposed above the substrate. The core device includes a first gate electrode having a bottom surface and a sidewall that define a first interior angle therebetween. The first interior angle is an obtuse angle. The I/O device includes a second gate electrode having a bottom surface and a sidewall that define a second interior angle therebetween. The second interior angle is greater than the first interior angle.