公开(公告)号：US09620615B2

公开(公告)日：2017-04-11

申请号：US14902516

申请日：2014-07-29

申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.

发明人： Xiaoshe Deng ,  Qiang Rui ,  Shuo Zhang ,  Genyi Wang

IPC分类号： H01L21/00 ,  H01L29/66 ,  H01L29/739 ,  H01L21/265 ,  H01L21/311 ,  H01L29/06

CPC分类号： H01L29/66333 ,  H01L21/26513 ,  H01L21/31111 ,  H01L29/0611 ,  H01L29/7395

摘要： An insulated gate bipolar transistor (IGBT) manufacturing method comprises the following steps: providing a semiconductor substrate of a first conducting type, the semiconductor substrate having a first major surface and a second major surface (100); forming a field-stop layer of a second conducting type on the first major surface of the semiconductor substrate (200); growing an oxide layer on the field-stop layer (300); removing the oxide layer from the field-stop layer (400); forming an epitaxial layer on the field-stop layer from which the oxide layer has been removed; and then manufacturing an IGBT on the epitaxial layer (600). Before regular manufacturing of an IGBT, the surface defects of a substrate material are eliminated as many as possible before epitaxy is formed, and the quality of an epitaxial layer is improved, thereby improving the quality of the whole IGBT.

公开(公告)号：US20170073224A1

公开(公告)日：2017-03-16

申请号：US15312146

申请日：2015-05-05

申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.

发明人： Yonggang HU ,  Guoping ZHOU

IPC分类号： B81C1/00

CPC分类号： B81C1/00619 ,  B81C1/00 ,  B81C2201/0133 ,  B81C2201/0142

摘要： An MEMS-based method for manufacturing a sensor comprises the steps of: forming a shallow channel (120) and a support beam (140) on a front surface of a substrate (100); forming a first epitaxial layer (200) on the front surface of the substrate (100) to seal the shallow channel (120); forming a suspended mesh structure (160) below the first epitaxial layer (200); and forming a deep channel (180) at a position on a back surface of the substrate (100) corresponding to the shallow channel (120), so that the shallow channel (120) is in communication with the deep channel (180). In the Method of manufacturing a MEMS-based sensor, when a shallow channel is formed on a front surface, a support beam of a mass block is formed, so the etching of a channel is easier to control, the process is snore precise. and the uniformity and the homogeneity of the formed support beam are better.

摘要翻译： 用于制造传感器的基于MEMS的方法包括以下步骤：在衬底（100）的前表面上形成浅沟道（120）和支撑梁（140）; 在所述衬底（100）的前表面上形成第一外延层（200）以密封所述浅沟道（120）; 在所述第一外延层（200）下方形成悬浮网状结构（160）; 以及在与所述浅通道（120）相对应的所述基板（100）的背表面上的位置处形成深通道（180），使得所述浅通道（120）与所述深通道（180）连通。 在制造基于MEMS的传感器的方法中，当在前表面上形成浅沟道时，形成质量块的支撑梁，因此通道的蚀刻更易于控制，工艺打鼾精确。 形成的支撑梁的均匀性和均匀性更好。

公开(公告)号：US20160372573A1

公开(公告)日：2016-12-22

申请号：US14902220

申请日：2014-07-23

申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.

发明人： Wanli Wang ,  Xiaoshe Deng ,  Genyi Wang ,  Xuan Huang

IPC分类号： H01L29/66 ,  H01L29/10 ,  H01L21/324 ,  H01L21/265 ,  H01L21/266 ,  H01L21/225 ,  H01L29/739 ,  H01L29/06

CPC分类号： H01L29/66348 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/324 ,  H01L29/063 ,  H01L29/1095 ,  H01L29/7397

摘要： A method for manufacturing an injection-enhanced insulated-gate bipolar transistor, comprising the following steps: an n-type substrate (12) is provided; a p-type doped layer (14) is formed on the n-type substrate (12); a hard layer (20) is formed on the p-type doped layer (14); a groove (40) extending to the n-type substrate (12) is formed by etching on the p-type doped layer (14); an n-type doped layer (50) is formed on the sidewalls and bottom of the groove (40); the hard layer (20) is removed; p-type impurities of the p-type doped layer (14) and n-type impurities of the n-type doped layer (50) are driven in together, where the p-type impurities are diffused to form a p-type base region (60), and the n-type impurities are diffused to form an n-type buffer layer (70); a gated oxide dielectric layer (80) is formed on the surface of the groove (40); and, a polysilicon layer (90) is deposited in the groove having formed therein the gate oxide dielectric layer (80). In the method for manufacturing the injection-enhanced insulated-gate bipolar transistor, the p-type doped layer (14) and the n-type doped layer (50) are driven in together to form the p-type base region (60) and the n-type buffer layer (70), as only one drive-in process is required, production cycle is shortened in comparison with a conventional method for manufacturing the injection-enhanced insulated-gate bipolar transistor.

摘要翻译： 一种用于制造注射增强型绝缘栅双极晶体管的方法，包括以下步骤：提供n型衬底（12）; 在n型衬底（12）上形成p型掺杂层（14）。 在p型掺杂层（14）上形成硬质层（20）。 通过蚀刻在p型掺杂层（14）上形成延伸到n型衬底（12）的凹槽（40）。 在凹槽（40）的侧壁和底部上形成n型掺杂层（50）; 去除硬层（20）; p型掺杂层（14）的p型杂质和n型掺杂层（50）的n型杂质一起被驱动，其中p型杂质被扩散以形成p型基极区域 （60），并且n型杂质扩散以形成n型缓冲层（70）; 在凹槽（40）的表面上形成栅极氧化物介电层（80）; 并且在其中形成有栅极氧化物介电层（80）的沟槽中沉积多晶硅层（90）。 在注入增强型绝缘栅双极晶体管的制造方法中，p型掺杂层（14）和n型掺杂层（50）一起被驱动以形成p型基极区（60）和 n型缓冲层（70）仅需要一个驱动工艺，与用于制造注射增强型绝缘栅双极晶体管的传统方法相比，生产周期缩短。

公开(公告)号：US09520400B2

公开(公告)日：2016-12-13

申请号：US14398849

申请日：2013-05-19

申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.

发明人： Shizhen Sun ,  Hao Fang ,  Yong Gu

IPC分类号： H01L27/105 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H01L27/115 ,  H01L21/283 ,  H01L29/423

CPC分类号： H01L27/1052 ,  H01L21/28273 ,  H01L21/283 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

摘要： A NOR flash memory and its manufacturing method are provided in the present disclosure, they are in the field of flash memory. In the manufacturing method, a mask dielectric layer is formed on a second polysilicon layer of a gate stack structure. In addition, part of the mask dielectric layer is etched patternedly to expose part of the second polysilicon layer which is close to a source. Furthermore, the exposed second polysilicon layer is self aligned to form a metal silicide layer. Thus in the NOR flash memory, an unetched mask dielectric layer is substantially located between a metal silicide layer and a drain contacting hole of the NOR flash memory. A drain current between the gate electrode and the drain electrode is small, the above manufacturing method is not complex, a process window is large, a side effect is small, which are advantageous to large scale production.

摘要翻译： 在本公开中提供了NOR闪存及其制造方法，它们在闪存的领域中。 在制造方法中，在栅极堆叠结构的第二多晶硅层上形成掩模电介质层。 此外，掩模介电层的一部分被图案化地蚀刻以暴露靠近源极的第二多晶硅层的部分。 此外，暴露的第二多晶硅层自对准以形成金属硅化物层。 因此，在NOR闪速存储器中，未蚀刻的掩模介电层基本上位于NOR闪存的金属硅化物层和漏极接触孔之间。 栅电极和漏电极之间的漏极电流小，上述制造方法不复杂，工艺窗口大，副作用小，有利于大规模生产。

公开(公告)号：US20160307995A1

公开(公告)日：2016-10-20

申请号：US14902284

申请日：2014-08-25

申请人： CSMC Technologies Fab1 Co., Ltd.

发明人： Shengrong Zhong ,  Dongfei Zhou ,  Xiaoshe Deng ,  Genyi Wang

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66 ,  H01L29/20 ,  H01L29/04 ,  H01L21/761 ,  H01L29/739 ,  H01L29/161

CPC分类号： H01L29/0623 ,  H01L21/761 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66333 ,  H01L29/6634 ,  H01L29/7395 ,  H01L29/7396

摘要： An insulated gate bipolar transistor (100) is provided. A substrate (10) of the insulated gate bipolar transistor (100) is of an N type. A P-type region (16) is disposed on a back of the N-type substrate. A back metal structure (18) is disposed on a back of the P-type region (16). A terminal protection ring is disposed in a terminal structure. A polysilicon gate (31) is disposed on a front surface of the substrate (10) in an active region. Sidewalls (72) are disposed at two sides of the polysilicon gate (31) on the substrate (10). An interlayer medium (81) covered with the polysilicon gate (31) and the sidewalls (72) is disposed on the substrate (10). The interlayer medium (81) is covered with a metal lead wire layer (91). An N-type carrier enhancement region (41) is disposed in the substrate (10) in the active region. A P-type body region (51) is disposed in the carrier enhancement region (41). An N-type heavily doped region (61) is disposed in the P-type body region (51). A P-type heavily doped region (71) is disposed in the N-type heavily doped region (61). An inward recessed shallow pit (62) with a depth of 0.15 to 0.3 micrometers is formed on a surface of the P-type heavily doped region (71). By disposing the carrier enhancement region (41), the carrier concentration of a channel can be increased and a forward voltage drop can be reduced; in addition, the shallow pit (62) can make a device obtain good impurity distribution and a large metal contact area, thereby improving the performance of the device.

摘要翻译： 提供绝缘栅双极晶体管（100）。 绝缘栅双极型晶体管（100）的基板（10）为N型。 P型区域（16）设置在N型基板的背面。 背面金属结构（18）设置在P型区域（16）的背面。 端子保护环设置在端子结构中。 在活性区域中的多晶硅栅极（31）设置在基板（10）的前表面上。 侧壁（72）设置在基板（10）上的多晶硅栅极（31）的两侧。 覆盖有多晶硅栅极（31）和侧壁（72）的层间介质（81）设置在基板（10）上。 层间介质（81）被金属引线层（91）覆盖。 在有源区域中的衬底（10）中设置有N型载流子增强区（41）。 P型体区域（51）设置在载体增强区域（41）中。 N型重掺杂区域（61）设置在P型体区域（51）中。 P型重掺杂区域（71）设置在N型重掺杂区域（61）中。 在P型重掺杂区域（71）的表面上形成深度为0.15至0.3微米的向内凹入的浅凹坑（62）。 通过设置载流子增强区域（41），可以增加沟道的载流子浓度并且可以减小正向压降; 此外，浅坑（62）可以使器件获得良好的杂质分布和大的金属接触面积，从而提高器件的性能。

公开(公告)号：US20160240659A1

公开(公告)日：2016-08-18

申请号：US15026193

申请日：2014-12-04

申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.

发明人： Guangsheng ZHANG ,  Sen ZHANG

IPC分类号： H01L29/78 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66

CPC分类号： H01L29/7816 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7835 ,  H01L29/7838

摘要： An LDMOS device, comprising a substrate (202), a gate electrode (211) on the substrate (202), a buried layer area in the substrate (202), and a diffusion layer on the buried layer area, wherein the buried layer area comprises a first buried layer (201) and a second buried layer (203), wherein the conduction types of impurities doped in the first buried layer (201) and the second buried layer (203) are opposite; the diffusion layer comprises a first diffusion area (205) and a second diffusion area (206), wherein the first diffusion area (205) is located on the first buried layer (201) and abuts against the first buried layer (201), and the second diffusion area (206) is located on the second buried layer (203) and abuts against the second buried layer (203); and the conduction types of impurities doped in the first buried layer (201) and the first diffusion area (205) are the same, and the conduction types of impurities doped in the second buried layer (203) and the second diffusion area (206) are the same. Additionally, also disclosed is a manufacturing method for the LDMOS device. A current path of the device in a conducting state is an area formed by the lower part of the second diffusion area (206) and the second buried layer (203) and is situated away from the surface of the device, so that the current capability of the device can be improved, the turn-on resistance can be reduced, and the reliability of the device can be improved.

摘要翻译： 一种LDMOS器件，包括衬底（202），在所述衬底（202）上的栅电极（211），所述衬底（202）中的掩埋层区域以及所述掩埋层区域上的扩散层，其中所述掩埋层区域 包括第一掩埋层（201）和第二掩埋层（203），其中掺杂在第一掩埋层（201）和第二掩埋层（203）中的杂质的传导类型相反; 所述扩散层包括第一扩散区域（205）和第二扩散区域（206），其中所述第一扩散区域（205）位于所述第一掩埋层（201）上并抵靠所述第一掩埋层（201），并且 所述第二扩散区域（206）位于所述第二掩埋层（203）上并与所述第二掩埋层（203）抵接; 并且掺杂在第一掩埋层（201）和第一扩散区域（205）中的杂质的导电类型相同，掺杂在第二掩埋层（203）和第二扩散区域（206）中的杂质的导电类型 是相同的。 此外，还公开了用于LDMOS器件的制造方法。 导通状态的器件的电流路径是由第二扩散区域（206）的下部和第二掩埋层（203）形成的并且远离器件表面的区域形成的区域，使得电流能力 的设备可以改善，可以降低导通电阻，并且可以提高器件的可靠性。

公开(公告)号：US20160233216A1

公开(公告)日：2016-08-11

申请号：US15023049

申请日：2014-12-03

申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.

发明人： Guangsheng ZHANG ,  Sen ZHANG

IPC分类号： H01L27/088 ,  H01L21/8236

摘要： A semiconductor device includes a substrate (110); a buried layer (120) formed on the substrate (110), a diffusion layer (130) formed on the buried layer (120), wherein the diffusion layer (130) includes a first diffusion region (132) and a second diffusion region (134), and an impurity type of the second diffusion region (134) is opposite to an impurity type of the first diffusion region (132); the diffusion layer (134) further comprises a plurality of third diffusion regions (136) formed in the second diffusion region, wherein an impurity type of the third diffusion region (136) is opposite to the impurity type of the second diffusion region (134); and a gate (144) formed on the diffusion layer (130).

摘要翻译： 半导体器件包括衬底（110）; 形成在所述衬底（110）上的掩埋层（120），形成在所述掩埋层（120）上的扩散层（130），其中所述扩散层（130）包括第一扩散区域（132）和第二扩散区域 134），并且所述第二扩散区（134）的杂质类型与所述第一扩散区（132）的杂质类型相反; 扩散层（134）还包括形成在第二扩散区域中的多个第三扩散区域（136），其中第三扩散区域（136）的杂质类型与第二扩散区域（134）的杂质类型相反， ; 和形成在扩散层（130）上的栅极（144）。

公开(公告)号：US09371224B2

公开(公告)日：2016-06-21

申请号：US14411931

申请日：2013-09-03

申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.

发明人： Jiale Su

IPC分类号： B81C1/00 ,  H01L21/308

CPC分类号： B81C1/00396 ,  B81B2203/033 ,  B81C1/00412 ,  B81C1/00619 ,  B81C1/00626 ,  B81C2201/0132 ,  H01L21/3086

摘要： A silicon etching method of etching a silicon substrate to form silicon trenches having different width dimensions includes: S1, providing a silicon substrate; S2, depositing a mask layer on the silicon substrate; S3, corroding the mask layer to form windows having different width dimensions, wherein a mask layer having a certain thickness is reserved at least at a bottom portion of a window having a non-minimum width dimension, such that all the silicon trenches have the same depth after step S4; and S4, corroding the mask layer at the bottom portion of the window and the silicon substrate to form the silicon trenches. The mask layer having a certain thickness is reserved at the bottom portion of the window having the non-minimum width dimension, a relatively large window is protected, and a relatively small window is etched first, so that the finally obtained silicon trenches have the same depth.

摘要翻译： 蚀刻硅衬底以形成具有不同宽度尺寸的硅沟槽的硅蚀刻方法包括：S1，提供硅衬底; S2，在硅衬底上沉积掩模层; S3，腐蚀掩模层以形成具有不同宽度尺寸的窗口，其中具有一定厚度的掩模层至少在具有非最小宽度尺寸的窗口的底部保留，使得所有硅沟槽具有相同的 步骤S4之后的深度; 和S4，腐蚀窗口底部的掩模层和硅衬底以形成硅沟槽。 具有一定厚度的掩模层被保留在具有非最小宽度尺寸的窗口的底部，相对较大的窗口被保护，并且首先蚀刻相对小的窗口，使得最终获得的硅沟槽具有相同的 深度。

公开(公告)号：US09252240B2

公开(公告)日：2016-02-02

申请号：US14436016

申请日：2013-12-31

申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.

发明人： Jian Xu ,  Min He ,  Shu Zhang ,  Zehuang Luo ,  Xiaojia Wu

IPC分类号： H01L21/762 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/311 ,  H01L29/40

CPC分类号： H01L29/66681 ,  H01L21/0217 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32 ,  H01L21/76213 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/408

摘要： A manufacturing method for a semiconductor device with a discrete field oxide structure is provided, the method includes: growing a first PAD oxide layer on the surface of a wafer; forming a first silicon nitride layer (302) on the first PAD oxide layer through deposition; defining a field region by photolithography and etching same to remove the first silicon nitride layer (302) located on the field region; performing an ion implantation process to the field region; performing field region oxidation to grow a field oxide layer (304); peeling off the first silicon nitride layer (302); wet-dipping the wafer to remove the first PAD oxide layer and a part of field oxide layer (304); growing a second PAD oxide layer on the surface of the wafer, and forming a second silicon nitride layer (312) on the second PAD oxide layer through deposition; defining a drift region by photolithography and etching same to remove the second silicon nitride layer (312) on the drift region; performing an ion implantation process to the drift region; and performing drift region oxidation to grow a drift region oxide layer (314). The above-mentioned method peels off the silicon nitride layer (302) after the growth of the field oxide layer (304) is finished, at this time, the length of a bird beak of field-oxide (304) can be optimized by adjusting a wet-dipping amount to solve the problem that the bird beak of field-oxide (304) is too long.

摘要翻译： 提供一种具有离散场氧化物结构的半导体器件的制造方法，该方法包括：在晶片表面上生长第一PAD氧化物层; 通过沉积在所述第一PAD氧化物层上形成第一氮化硅层（302）; 通过光刻法定义场区域并进行蚀刻以去除位于场区域上的第一氮化硅层（302）; 对场区进行离子注入工艺; 进行场区氧化以生长场氧化物层（304）; 剥离第一氮化硅层（302）; 湿浸湿晶片以去除第一PAD氧化物层和一部分场氧化物层（304）; 在所述晶片的表面上生长第二PAD氧化物层，并且通过沉积在所述第二PAD氧化物层上形成第二氮化硅层（312）; 通过光刻法定义漂移区域并进行蚀刻以去除漂移区域上的第二氮化硅层（312）; 对漂移区域进行离子注入工艺; 以及进行漂移区氧化以生长漂移区氧化物层（314）。 上述方法在场氧化物层（304）的生长完成之后，剥离氮化硅层（302），此时可以通过调整场氧化物（304）的鸟喙的长度来优化 用于解决场氧化物（304）的鸟喙太长的问题的湿浸量。

公开(公告)号：US20150233965A1

公开(公告)日：2015-08-20

申请号：US14435925

申请日：2013-08-30

申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.

发明人： Meihan Guo ,  Xinwei Zhang ,  Changfeng Xia ,  Wei Su

IPC分类号： G01P15/125 ,  B81B7/02 ,  H02N1/08

CPC分类号： G01P15/125 ,  B81B7/02 ,  G01P2015/0837 ,  H01G5/16 ,  H02N1/08

摘要： A parallel plate capacitor includes a first polar plate (10), and a second polar plate disposed opposite to the first polar plate (10). The parallel plate capacitor further includes at least a pair of sensitive units disposed on a substrate forming the first polar plate (10); the sensitive units includes sensitive elements (21a, 21b, 22a, 22b) and element connecting arms (23a, 23b, 24a, 24b) connecting the sensitive elements (21a, 21b, 22a, 22b) to the first polar plate (10). The parallel plate capacitor further includes anchoring bases (30, 31, 32, 33) disposed on a substrate where the second polar plate is located; the anchoring bases (30, 31, 32, 33) are connected to the element connecting arms (23a, 23b, 24a, 24b) via cantilever beams (30a, 30b, 31a, 31b, 32a, 32b, 33a, 33b); each element connecting arm (23a, 23b, 24a, 24b) is connected to at least two anchoring bases (30, 31, 32, 33), which are symmetric with respect to the element connecting arm. The parallel plate capacitor is more likely to be influenced by an external factor, thus being more likely to experience capacitance change. An acceleration sensor including the parallel plate capacitor is also provided.

摘要翻译： 平行板电容器包括第一极板（10）和与第一极板（10）相对设置的第二极板。 平行板电容器还包括至少一对设置在形成第一极板（10）的基板上的敏感单元。 敏感单元包括将敏感元件（21a，21b，22a，22b）连接到第一极板（10）的敏感元件（21a，21b，22a，22b）和元件连接臂（23a，23b，24a，24b）。 平行板电容器还包括设置在第二极板所在的基板上的固定基座（30,31,32,33）。 通过悬臂梁（30a，30b，31a，31b，32a，32b，33a，33b）将锚定基座（30,31,32,33）连接到元件连接臂（23a，23b，24a，24b） 每个元件连接臂（23a，23b，24a，24b）连接到至少两个相对于元件连接臂对称的锚定基座（30,31,32,33）。 并联平板电容更可能受到外部因素的影响，因此更容易发生电容变化。 还提供了包括平行板电容器的加速度传感器。