公开(公告)号：US20170358657A1

公开(公告)日：2017-12-14

申请号：US15541155

申请日：2015-09-28

申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.

发明人： Feng HUANG ,  Guangtao HAN ,  Guipeng SUN ,  Feng LIN ,  Longjie ZHAO ,  Huatang LIN ,  Bing ZHAO ,  Lixiang LIU ,  Liangliang PING ,  Fengying CHEN

IPC分类号： H01L29/66 ,  H01L29/40 ,  H01L21/311 ,  H01L29/739 ,  H01L29/06 ,  H01L21/02 ,  H01L21/265

CPC分类号： H01L29/66325 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02318 ,  H01L21/26513 ,  H01L21/31116 ,  H01L29/0653 ,  H01L29/408 ,  H01L29/7393 ,  H01L29/78

摘要： The present invention relates to a method for manufacturing a laterally insulated-gate bipolar transistor, comprising: providing a wafer having an N-type buried layer (10), an STI (40), and a first N well (22)/a first P well (24) which are formed successively from above a substrate; depositing and forming a high-temperature oxide film on the first N well (22) of the wafer; performing thermal drive-in on the wafer and performing photoetching and etching on the high-temperature oxide film to form a mini oxide layer (60); performing photoetching and ion implantation so as to form a second N well (32) inside the first N well (22) and second P wells (34) inside the first N well (22) and the first P well (24); then successively forming a gate oxide layer and a polysilicon gate (72), wherein one end of the gate oxide layer and the polysilicon gate (72) extends onto the second P well (34) inside the first N well (22), and the other end extends onto the mini oxide layer (60) on the second N well (32); and photoetching and injecting N-type ions between the mini oxide layer (60) and the STI (40) adjacent to the mini oxide layer (60) to form a drain electrode, and at the same time forming a source electrode (51) inside the second P well (34).

公开(公告)号：US20170352749A1

公开(公告)日：2017-12-07

申请号：US15538450

申请日：2015-09-10

申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.

发明人： Shukun QI

IPC分类号： H01L29/739 ,  H01L29/08

CPC分类号： H01L29/7394 ,  H01L29/0834 ,  H01L29/7393

摘要： A lateral insulated gate bipolar transistor comprises a substrate (10); an anode terminal located on the substrate, comprising: an N-type buffer region (51) located on the substrate (10); a P well (53) located in the N-type buffer region; an N-region (55) located in the P well (53); two P+ shallow junctions (57) located on a surface of the P well (53); and an N+ shallow junction (59) located between the two P+ shallow junctions (57); a cathode terminal located on the substrate; a draft region (30) between the anode terminal and cathode terminal; and a gate (62) between the anode terminal and cathode terminal.

公开(公告)号：US09780084B2

公开(公告)日：2017-10-03

申请号：US15055613

申请日：2016-02-28

申请人： CSMC Technologies Fab1 Co., Ltd.

发明人： Yonghai Hu ,  Meng Dai ,  Zhongyu Lin ,  Guangyang Wang

IPC分类号： H01L21/04 ,  H01L27/02 ,  H01L29/66 ,  H01L29/87 ,  H01L21/762 ,  H01L21/8232 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3205 ,  H01L29/40

CPC分类号： H01L27/0255 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/26513 ,  H01L21/32055 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/8232 ,  H01L27/0248 ,  H01L29/402 ,  H01L29/66121 ,  H01L29/87

摘要： An electrostatic discharge protection structure includes: substrate of a first type of conductivity, well region of a second type of conductivity, substrate contact region in the substrate and of the first type of conductivity, well contact region in the well region and of the second type of conductivity, substrate counter-doped region between the substrate contact region and the well contact region and of the second type of conductivity, well counter-doped region between the substrate contact region and the well contact region and of the first type of conductivity, communication region at a lateral junction between the substrate and the well region, first isolation region between the substrate counter-doped region and the communication region, second isolation region between the well counter-doped region and the communication region, oxide layer having one end on the first isolation region and another end on the substrate, and field plate structure on the oxide layer.

公开(公告)号：US20170163271A1

公开(公告)日：2017-06-08

申请号：US15325855

申请日：2015-06-30

申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.

发明人： Huagang WU

IPC分类号： H03L7/16

CPC分类号： G06F1/0321 ,  G06F1/022 ,  H03L7/16

摘要： A direct digital frequency synthesis method comprises the following steps: calculating, by a phase accumulation module, a first phase according to a frequency synthesis word (S101); finding an amplitude value by a preset sinusoidal lookup table according to the first phase (S102); finding a second phase by a preset phase lookup table according to the amplitude value (S103); if the second phase is less than the first phase, adjusting and outputting the amplitude value (S105); or else, outputting the original amplitude value (S106); and performing, by a digital-to-analog converter, a digital-to-analog conversion according to the output amplitude value to obtain a sinusoidal wave (S107); wherein, for a N-bit phase accumulation module and a D-bit digital-to-analog converter, the preset phase lookup table has 2D−1-1 phase boundary value records corresponding to 0˜2D−1-2 amplitudes, each phase boundary value is stored in N-2 bits. A direct digital frequency synthesizer applying the above method is also disclosed.

公开(公告)号：US09673193B2

公开(公告)日：2017-06-06

申请号：US14902519

申请日：2014-08-19

申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.

发明人： Shuo Zhang ,  Qiang Rui ,  Genyi Wang ,  Xiaoshe Deng

IPC分类号： H01L27/06 ,  H01L29/66 ,  H01L29/739 ,  H01L21/3065 ,  H01L21/265 ,  H01L21/304 ,  H01L29/10 ,  H01L29/06

CPC分类号： H01L27/0664 ,  H01L21/263 ,  H01L21/26513 ,  H01L21/304 ,  H01L21/3065 ,  H01L29/0638 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/7395

摘要： A manufacturing method for reverse conducting insulated gate bipolar transistor, the manufacturing method is characterized by the use of polysilicon for filling in grooves on the back of a reverse conducting insulated gate bipolar transistor. The parameters of reverse conducting diodes on the back of the reverse conducting insulated gate bipolar transistor can be controlled simply by controlling the doping concentration of the polysilicon accurately, indicating relatively low requirements for process control. The reverse conducting insulated gate bipolar transistor manufacturing method is relatively low in requirements for process control and relatively small in manufacturing difficulty.

公开(公告)号：US09583587B2

公开(公告)日：2017-02-28

申请号：US14902220

申请日：2014-07-23

申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.

发明人： Wanli Wang ,  Xiaoshe Deng ,  Genyi Wang ,  Xuan Huang

IPC分类号： H01L21/33 ,  H01L21/22 ,  H01L21/38 ,  H01L29/66 ,  H01L29/739 ,  H01L29/10 ,  H01L29/06 ,  H01L21/265 ,  H01L21/266 ,  H01L21/225 ,  H01L21/324

CPC分类号： H01L29/66348 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/324 ,  H01L29/063 ,  H01L29/1095 ,  H01L29/7397

摘要： A method for manufacturing an injection-enhanced insulated-gate bipolar transistor, comprising the following steps: an n-type substrate (12) is provided; a p-type doped layer (14) is formed on the n-type substrate (12); a hard layer (20) is formed on the p-type doped layer (14); a groove (40) extending to the n-type substrate (12) is formed by etching on the p-type doped layer (14); an n-type doped layer (50) is formed on the sidewalls and bottom of the groove (40); the hard layer (20) is removed; p-type impurities of the p-type doped layer (14) and n-type impurities of the n-type doped layer (50) are driven in together, where the p-type impurities are diffused to form a p-type base region (60), and the n-type impurities are diffused to form an n-type buffer layer (70); a gated oxide dielectric layer (80) is formed on the surface of the groove (40); and, a polysilicon layer (90) is deposited in the groove having formed therein the gate oxide dielectric layer (80). In the method for manufacturing the injection-enhanced insulated-gate bipolar transistor, the p-type doped layer (14) and the n-type doped layer (50) are driven in together to form the p-type base region (60) and the n-type buffer layer (70), as only one drive-in process is required, production cycle is shortened in comparison with a conventional method for manufacturing the injection-enhanced insulated-gate bipolar transistor.

摘要翻译： 一种用于制造注射增强绝缘栅双极晶体管的方法，包括以下步骤：提供n型衬底（12）; 在n型衬底（12）上形成p型掺杂层（14）。 在p型掺杂层（14）上形成硬质层（20）。 通过蚀刻在p型掺杂层（14）上形成延伸到n型衬底（12）的沟槽（40）。 在凹槽（40）的侧壁和底部上形成n型掺杂层（50）; 去除硬层（20）; p型掺杂层（14）的p型杂质和n型掺杂层（50）的n型杂质一起被驱动，其中p型杂质被扩散以形成p型基极区域 （60），并且n型杂质扩散以形成n型缓冲层（70）; 在凹槽（40）的表面上形成栅极氧化物介电层（80）; 并且在其中形成有栅极氧化物介电层（80）的沟槽中沉积多晶硅层（90）。 在注入增强型绝缘栅双极晶体管的制造方法中，p型掺杂层（14）和n型掺杂层（50）一起被驱动以形成p型基极区（60）和 n型缓冲层（70）仅需要一个驱动工艺，与用于制造注射增强型绝缘栅双极晶体管的传统方法相比，生产周期缩短。

公开(公告)号：US09580301B2

公开(公告)日：2017-02-28

申请号：US14411537

申请日：2013-06-29

申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.

发明人： Dan Dai ,  Xinwei Zhang ,  Guoping Zhou ,  Changfeng Xia

IPC分类号： B81B7/00 ,  B81C1/00

CPC分类号： B81C1/00825 ,  B81B7/0029 ,  B81C1/0038 ,  B81C2201/0167 ,  B81C2201/053

摘要： A MEMS chip (100) includes a silicon substrate layer (110), a first oxidation layer (120) and a first thin film layer (130). The silicon substrate layer includes a front surface (112) for a MEMS process and a rear surface (114), both the front surface and the rear surface being polished surfaces. The first oxidation layer is mainly made of silicon dioxide and is formed on the rear surface of the silicon substrate layer. The first thin film layer is mainly made of silicon nitride and is formed on the surface of the first oxidation layer. In the above MEMS chip, by sequentially laminating a first oxidation layer and a first thin film layer on the rear surface of a silicon substrate layer, the rear surface is effectively protected to prevent the scratch damage in the course of a MEMS process. A manufacturing method for the MEMS chip is also provided.

摘要翻译： MEMS芯片（100）包括硅衬底层（110），第一氧化层（120）和第一薄膜层（130）。 硅衬底层包括用于MEMS工艺的前表面（112）和后表面（114），前表面和后表面都是​​抛光表面。 第一氧化层主要由二氧化硅制成，并形成在硅衬底层的后表面上。 第一薄膜层主要由氮化硅制成，并且形成在第一氧化层的表面上。 在上述MEMS芯片中，通过在硅衬底层的后表面依次层叠第一氧化层和第一薄膜层，有效地保护后表面以防止在MEMS工艺过程中的划痕损伤。 还提供了一种用于MEMS芯片的制造方法。

公开(公告)号：US20160380048A1

公开(公告)日：2016-12-29

申请号：US14902432

申请日：2014-08-25

申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.

发明人： Shengrong Zhong ,  Dongfei Zhou ,  Xiaoshe Deng ,  Genyi Wang

IPC分类号： H01L29/06 ,  H01L29/739 ,  H01L29/10 ,  H01L21/761 ,  H01L29/16 ,  H01L29/20 ,  H01L29/161 ,  H01L29/04 ,  H01L29/66 ,  H01L29/40

CPC分类号： H01L29/0623 ,  H01L21/761 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/20 ,  H01L29/401 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66333 ,  H01L29/6634 ,  H01L29/7395 ,  H01L29/7396

摘要： A method for manufacturing an insulated gate bipolar transistor (100) comprises: providing a substrate (10), forming a field oxide layer (20) on a front surface of the substrate (10), and forming a terminal protection ring (23); performing photoetching and etching on the active region field oxide layer (20) by using an active region photomask, introducing N-type ions into the substrate (10) by using a photoresist as a mask film; depositing and forming a polysilicon gate (31) on the etched substrate (10) of the field oxide layer (20), and forming a protection layer on the polysilicon gate (31); performing junction pushing on an introduction region of the N-type ions, and then forming a carrier enhancement region (41); performing photoetching by using a P well photomask, introducing P-type ions into the carrier enhancement region (41), and performing junction pushing and then forming a P-body region; performing, by means of the polysilicon gate, self-alignment introduction of N-type ions into the P-body region, and performing junction pushing and then forming an N-type heavily doped region; forming sidewalls on two sides of the polysilicon gate, introducing P-type ions into the N-type heavily doped region, and performing junction pushing and then forming a P-type heavily doped region; and removing the protection layer, and then performing introduction and doping of the polysilicon gate. The method reduces a forward voltage drop disposing the carrier enhancement region.

摘要翻译： 一种用于制造绝缘栅双极晶体管（100）的方法，包括：提供衬底（10），在衬底（10）的前表面上形成场氧化物层（20），并形成端子保护环（23）; 通过使用有源区光掩模对有源区域氧化物层（20）进行光刻和蚀刻，通过使用光致抗蚀剂作为掩模膜将N型离子引入到衬底（10）中; 在所述场氧化物层（20）的蚀刻衬底（10）上沉积和形成多晶硅栅极（31），并在所述多晶硅栅极（31）上形成保护层; 在N型离子的导入区域上进行接合，然后形成载流子增强区域（41）。 通过使用P阱光掩模进行光蚀刻，将P型离子引入载体增强区域（41）中，并执行连接推动然后形成P体区域; 通过多晶硅栅极进行N型离子的自对准引入到P体区域中，并进行结压并形成N型重掺杂区域; 在所述多晶硅栅极的两侧形成侧壁，将P型离子引入所述N型重掺杂区域中，并执行结推进，然后形成P型重掺杂区域; 并去除保护层，然后进行多晶硅栅极的引入和掺杂。 该方法减少了设置载流子增强区域的正向压降。

公开(公告)号：US09466388B2

公开(公告)日：2016-10-11

申请号：US15025846

申请日：2014-10-10

申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.

发明人： Shuming Guo ,  Guoyi Zong

IPC分类号： G11C7/00 ,  G11C16/26 ,  G11C16/24 ,  G11C16/32

CPC分类号： G11C16/26 ,  G11C16/24 ,  G11C16/32

摘要： A readout circuit with a self-detection circuit and a control method therefor. The circuit comprises a pre-charging circuit and a control circuit, the pre-charging circuit and the control circuit being connected to a first node and used for charging a memory unit. The readout circuit also comprises a detection circuit, the detection circuit and the pre-charging circuit being connected to the first node. The detection circuit comprises a third NOT gate, a fourth NOT gate, a first NAND gate, a sixth NOT gate, a first trigger and an eighth NOT gate. In such a manner of detecting the reversal of the first NOT gate through the reversal of the third NOT gate, the charging duration of the first node (A) can be greatly reduced, thereby reducing the reading duration of the whole circuit. At the same time, the re-occurrence of a state of charging the circuit can be avoided after pre-charging has ended.

摘要翻译： 一种具有自检电路及其控制方法的读出电路。 该电路包括预充电电路和控制电路，预充电电路和控制电路连接到第一节点并用于对存储器单元充电。 读出电路还包括检测电路，检测电路和预充电电路连接到第一节点。 检测电路包括第三NOT门，第四NOT门，第一NAND门，第六NOT门，第一触发器和第八NOT门。 以这样的方式，通过第三非门的反相来检测第一非门的反向，可以大大减少第一节点（A）的充电持续时间，从而减少整个电路的读取持续时间。 同时，在预充电结束之后可以避免电路充电状态的再次发生。

公开(公告)号：US09431308B2

公开(公告)日：2016-08-30

申请号：US14436033

申请日：2013-12-31

申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.

发明人： Anna Zhang ,  Xiaoming Li

IPC分类号： H01L21/66 ,  H01L21/308 ,  H01L21/3065

CPC分类号： H01L22/12 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3083 ,  H01L22/20

摘要： A critical dimension compensating method of a deep trench etching process includes: obtaining an etching critical dimension difference; compensating an masking layer layout for wafer etching according to a distance between an etching position and the center position of the wafer, and the etching critical dimension difference; and performing a deep trench etching to the wafer according to the compensated masking layer layout. The dimension of the etching patterns of the masking layer layout is compensated by using half of the critical dimension difference as the compensation value, such that the etch rate difference and the etching dimension difference caused by uneven distribution of the critical dimension at different wafer locations during the deep trench etching process are improved, thus greatly improving the uniformity of the critical dimension of the deep trench etching structure.

摘要翻译： 深沟槽蚀刻工艺的关键尺寸补偿方法包括：获得蚀刻临界尺寸差; 根据蚀刻位置和晶片的中心位置之间的距离和蚀刻临界尺寸差补偿用于晶片蚀刻的掩模层布局; 以及根据补偿的掩模层布局对晶片执行深沟槽蚀刻。 通过使用临界尺寸差的一半作为补偿值来补偿掩模层布局的蚀刻图案的尺寸，使得由不同晶片位置的临界尺寸不均匀分布引起的蚀刻速率差和蚀刻尺寸差异 深沟槽蚀刻工艺得到改善，从而大大提高了深沟槽蚀刻结构的临界尺寸的均匀性。