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公开(公告)号：US3780320A
公开(公告)日：1973-12-18
申请号：US3780320D
申请日：1971-12-20
Applicant: IBM
Inventor： DORLER J , FORNERIS J , SWIETEK D
CPC classification number: H01L27/1021 , G11C17/00 , G11C17/06 , G11C17/08 , H01L21/00 , H01L27/00 , Y10S257/926
Abstract: A monolithic Schottky barrier diode read-only memory comprising a semiconductor substrate having more than one separate and distinctly functional integrated circuit means located thereon. A plurality of Schottky barrier diodes comprising a more than one metal system contact the semi-conductor substrate for forming a plurality of Schottky barrier diode junctions. A separate Schottky barrier diode comprising a corresponding more than one metal system is incorporated into the other separate and distinctly functional integrated circuit means for addressing the Schottky barrier diode and sensing information therefrom. Interconnection metallurgy corresponding to the more than one metal system connects the plurality of separate and distinctly functional integrated circuit means and forms a continuous electrical path with the more than one metal system forming the Schottky barrier diodes.
Abstract translation: 单片肖特基势垒二极管只读存储器，其包括具有位于其上的多于一个分离且明显功能的集成电路装置的半导体衬底。 包括多于一个金属系统的多个肖特基势垒二极管与半导体衬底接触以形成多个肖特基势垒二极管结。 包括相应的多于一个金属系统的单独的肖特基势垒二极管被并入到用于寻址肖特基势垒二极管和从其感测信息的另一个分离和明显功能的集成电路装置中。 对应于多于一个金属系统的互连冶金连接多个独立和明显功能的集成电路装置，并与形成肖特基势垒二极管的多于一个的金属系统形成连续的电路径。
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公开(公告)号：US3739355A
公开(公告)日：1973-06-12
申请号：US3739355D
申请日：1971-05-28
Applicant: BURROUGHS CORP
Inventor： RADCLIFFE A
Abstract: A sense amplifier for use in the interrogation of a phototransistor matrix employs an electronically controlled impedance in parallel with the load resistor of each column. The electronically controlled impedance substantially reduces the time constant of electrical noise resulting from row selection. Additionally, a balancing capacitor functions to cancel the transient which results from the switching of the controlled impedance.
Abstract translation: 用于询问光电晶体管矩阵的读出放大器采用与每列负载电阻并联的电子控制阻抗。 电子控制的阻抗大大减少了由行选择引起的电噪声的时间常数。 此外，平衡电容器用于消除由受控阻抗切换引起的瞬变。
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公开(公告)号：US3713885A
公开(公告)日：1973-01-30
申请号：US3713885D
申请日：1970-03-02
Applicant: HONEYWELL BULL SOC IND
Inventor： GALLARD J , LAGADEC I , BETREMIEUX P , FEISSEL H
CPC classification number: G11C29/78 , G11C17/00 , G11C29/832
Abstract: A memory matrix and the process for fabricating said matrix, wherein a conductive array is formed of two mutually orthogonal and insulated sets of parallel conductive metallic bands, each band being formed of two superposed conductive strips, the lower strip of each band of the first set passing through an opening in the lower strip of each band of the second set and the upper strip of each band of the second set passing through an opening in the upper strip of each band of the first set, and wherein coupling elements selectively couple bands of one set to bands of the other set.
Abstract translation: 一种存储矩阵和用于制造所述矩阵的过程，其中导电阵列由两个相互正交和绝缘的平行导电金属带集合形成，每个带由两个重叠的导电条形成，第一组的每个带的下条 穿过第二组的每个带的下条中的开口，并且穿过第二组的每个带的每个带的上带通过第一组的每个带的上带中的开口，并且其中耦合元件选择性地耦合 一组设置为另一组的乐队。
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公开(公告)号：US3315230A
公开(公告)日：1967-04-18
申请号：US32795563
申请日：1963-12-04
Applicant: UNIVERSAL CONTROLS INC
Inventor： NEWTON WEINGART RICHARD ISAAC
CPC classification number: G07F7/08 , G06Q20/40 , G06Q20/4037 , G11C17/00
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Patent Agency Ranking
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公开(公告)号：US09921761B2
公开(公告)日：2018-03-20
申请号：US15343576
申请日：2016-11-04
Applicant: Seagate Technology LLC
Inventor： Radoslav Danilak
IPC: G11C11/34 , G06F3/06 , G11C16/34 , G06F12/02 , G11C29/04 , G06F11/10 , G11C16/10 , G11C16/14 , G11C16/26 , G11C29/52 , G11C14/00 , G11C17/00
CPC classification number: G06F3/0616 , G06F3/0608 , G06F3/0631 , G06F3/064 , G06F3/0649 , G06F3/0652 , G06F3/0653 , G06F3/0659 , G06F3/0673 , G06F11/1072 , G06F12/023 , G06F12/0246 , G06F2212/1044 , G06F2212/7201 , G06F2212/7202 , G06F2212/7205 , G06F2212/7211 , G11C14/009 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/349 , G11C16/3495 , G11C17/00 , G11C29/04 , G11C29/52
Abstract: The present disclosure relates to examples of controlling recycling of blocks of memory. In one example implementation according to aspects of the present disclosure, a method comprises allocating at least one block of memory selected from a subset of blocks to be written in accordance with an equalizing technique to equalize a variation between blocks of memory based on at least one factor. The method further comprises resupplying the subset of blocks.
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公开(公告)号：US09805800B1
公开(公告)日：2017-10-31
申请号：US15410974
申请日：2017-01-20
Applicant: SK hynix Inc.
Inventor： Hyun Min Song
CPC classification number: G11C16/10 , G11C16/00 , G11C16/0433 , G11C16/0483 , G11C16/24 , G11C16/30 , G11C17/00 , G11C17/18
Abstract: An EPROM device includes bit lines branching from a supply voltage line, a first group of enablement signal lines intersecting the bit lines, unit cells respectively located at cross points of the bit lines and the first group of enablement signal lines, pass transistors, load transistors, comparators, and enablement signal generators. One of the pass transistors and one of the load transistors are coupled in series between the supply voltage line and each of the bit lines. Each of the comparators receives voltages of both ends of any one of the load transistors to generate an output signal. Each of the enablement signal generators receives one of the output signals of the comparators and one of a second group of enablement signals and outputs one of a third group of enablement signals to turn off one of the pass transistors responsive to a program current reaching a reference value.
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公开(公告)号：US09805771B2
公开(公告)日：2017-10-31
申请号：US14190435
申请日：2014-02-26
Applicant: Infineon Technologies AG
Inventor： Ulrich Loibl , Thomas Kern
CPC classification number: G11C7/06 , G11C7/062 , G11C7/065 , G11C11/16 , G11C11/1659 , G11C11/1673 , G11C11/4091 , G11C13/00 , G11C16/349 , G11C17/00 , G11C29/028 , G11C29/50
Abstract: A method is suggested for determining a state of a cell structure, wherein the cell structure includes several memory cells, the method includes: (i) detecting a first condition in a predetermined number of memory cells; and (ii) determining the state of the cell structure by assigning a second condition to the memory cells that do not show the first condition.
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公开(公告)号：US20170098632A1
公开(公告)日：2017-04-06
申请号：US15381073
申请日：2016-12-15
Applicant: Guobiao ZHANG
Inventor： Guobiao ZHANG
IPC: H01L25/065 , G11C8/06 , G11C5/02 , H01L27/112
CPC classification number: G11C5/02 , G11C8/06 , G11C11/56 , G11C17/00 , G11C17/06 , G11C17/16 , G11C17/18 , G11C2213/71 , H01L21/8221 , H01L21/8229 , H01L25/0657 , H01L27/1021 , H01L27/11206 , H01L27/1128 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/73265 , H01L2225/06506 , H01L2225/06562 , H01L2225/06582 , H01L2924/181 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
Abstract: The present invention discloses a three-dimensional 3D-oP (three-dimensional offset-printed memory)-based package (3D2-oP). The mask-patterns for different dice in a same 3D2-oP package are merged onto a same data-mask. At different printing steps, a wafer is offset by different values with respect to the data-mask. Accordingly, data-patterns from a same data-mask are printed into different dice in a same 3D2-oP package.
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