公开(公告)号：US11894276B2

公开(公告)日：2024-02-06

申请号：US17461849

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Wei Lee ,  Wen-Hung Huang ,  Kuo-Feng Yu ,  Jian-Hao Chen ,  Hsueh-Ju Chen ,  Zoe Chen

IPC: H01L21/8238 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/311 ,  H01L27/088

CPC classification number: H01L21/823857 ,  H01L21/31105 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823821 ,  H01L27/088 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: A method includes providing a structure having a first channel member and a second channel member over a substrate. The first channel member is located in a first region of the structure and the second channel member is located in a second region of the structure. The method also includes forming a first oxide layer over the first channel member and a second oxide layer over the second channel member, forming a first dielectric layer over the first oxide layer and a second dielectric layer over the second oxide layer, and forming a capping layer over the second dielectric layer but not over the first dielectric layer. The method further includes performing an annealing process to increase a thickness of the second oxide layer under the capping layer.

公开(公告)号：US20230395432A1

公开(公告)日：2023-12-07

申请号：US17832582

申请日：2022-06-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Yuan Chen ,  Kuo-Feng Yu ,  Jian-Hao Chen ,  Chih-Yu Hsu ,  Yao-Teng Chuang ,  Shan-Mei Liao

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/775 ,  H01L29/66

CPC classification number: H01L21/823462 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/6684 ,  H01L29/66742 ,  H01L29/78391

Abstract: Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes providing a workpiece comprising a first channel member directly over a first region of a substrate and a second channel member directly over the first channel member, the first channel member being vertically spaced apart from the second channel member, conformally forming a dielectric layer over the workpiece, conformally depositing a dipole material layer over the dielectric layer, after the depositing of the dipole material layer, performing a thermal treatment process to the workpiece, after the performing of the thermal treatment process, selectively removing the dipole material layer, and forming a gate electrode layer over the dielectric layer.

公开(公告)号：US20230187535A1

公开(公告)日：2023-06-15

申请号：US17831130

申请日：2022-06-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Jiun Peng ,  Hsuan-Chih Wu ,  Cheng-Chung Chang ,  Shu-Han Chen ,  Hsiu-Hao Tsao ,  Min-Chia Lee ,  Kai-Min Chien ,  Ming-Chang Wen ,  Kuo-Feng Yu ,  Chang-Jhih Syu

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/6656 ,  H01L29/42392 ,  H01L21/823418 ,  H01L21/823468 ,  H01L29/0673 ,  H01L21/823412 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method for manufacturing the semiconductor structure includes forming a fin structure protruding from a substrate, and the fin structure includes first semiconductor material layers and second semiconductor material layers alternately stacked. The method also includes forming a dummy gate structure across the fin structure and forming a gate spacer on a sidewall of the dummy gate structure. The method also includes partially oxidizing the gate spacer to form an oxide layer and removing the oxide layer to form a modified gate spacer. The method also includes removing the first semiconductor material layers to form gaps and forming a gate structure in the gaps to wrap around the second semiconductor material layers and over the second semiconductor material layers to cover the modified gate spacer.

公开(公告)号：US20230061018A1

公开(公告)日：2023-03-02

申请号：US17461849

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Wei Lee ,  Wen-Hung Huang ,  Kuo-Feng Yu ,  Jian-Hao Chen ,  Hsueh-Ju Chen ,  Zoe Chen

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/311

Abstract: A method includes providing a structure having a first channel member and a second channel member over a substrate. The first channel member is located in a first region of the structure and the second channel member is located in a second region of the structure. The method also includes forming a first oxide layer over the first channel member and a second oxide layer over the second channel member, forming a first dielectric layer over the first oxide layer and a second dielectric layer over the second oxide layer, and forming a capping layer over the second dielectric layer but not over the first dielectric layer. The method further includes performing an annealing process to increase a thickness of the second oxide layer under the capping layer.

公开(公告)号：US20220285514A1

公开(公告)日：2022-09-08

申请号：US17466501

申请日：2021-09-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Wei Chen ,  Wei Cheng Hsu ,  Hui-Chi Chen ,  Jian-Hao Chen ,  Kuo-Feng Yu ,  Shih-Hang Chiu ,  Wei-Cheng Wang ,  Kuan-Ting Liu ,  Yen-Ju Chen ,  Chun-Chih Cheng ,  Wei-Chen Hsiao

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/40

Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.

公开(公告)号：US20220278218A1

公开(公告)日：2022-09-01

申请号：US17186472

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Wei Chen ,  Wei Cheng Hsu ,  Hui-Chi Chen ,  Jian-Hao Chen ,  Kuo-Feng Yu ,  Shih-Hang Chiu ,  Wei-Cheng Wang ,  Yen-Ju Chen

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/786 ,  H01L29/49 ,  H01L21/8238

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes a first channel members being vertically stacked, a second channel members being vertically stacked, an n-type work function layer wrapping around each of the first channel members, a first p-type work function layer over the n-type work function layer and wrapping around each of the first channel members, a second p-type work function layer wrapping around each of the second channel members, a third p-type work function layer over the second p-type work function layer and wrapping around each of the second channel members, and a gate cap layer over a top surface of the first p-type work function layer and a top surface of the third p-type work function layer such that the gate cap layer electrically couples the first p-type work function layer and the third p-type work function layer.

公开(公告)号：US20220262928A1

公开(公告)日：2022-08-18

申请号：US17464091

申请日：2021-09-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yung-Hsiang Chan ,  Shan-Mei Liao ,  Wen-Hung Huang ,  Jian-Hao Chen ,  Kuo-Feng Yu ,  Mei-Yun Wang

IPC: H01L29/66 ,  H01L29/417 ,  H01L27/088 ,  H01L29/78

Abstract: A method includes forming a dielectric layer on a semiconductor workpiece, forming a first patterned layer of a first dipole material on the dielectric layer, and performing a first thermal drive-in operation at a first temperature to form a diffusion feature in a first portion of the dielectric layer beneath the first patterned layer. The method also includes forming a second patterned layer of a second dipole material, where a first section of the second patterned layer is on the diffusion feature and a second patterned layer is offset from the diffusion feature. The method further includes performing a second thermal drive-in operation at a second temperature, where the second temperature is less than the first temperature. The method additionally includes forming a gate electrode layer on the dielectric layer.

公开(公告)号：US11329139B2

公开(公告)日：2022-05-10

申请号：US16514373

申请日：2019-07-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chun Hsiung Tsai ,  Kuo-Feng Yu ,  Yu-Ming Lin ,  Clement Hsingjen Wann

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/08 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/266

Abstract: A method of manufacturing a semiconductor device includes: providing a substrate comprising a surface; depositing a first dielectric layer and a second dielectric layer over the substrate; forming a dummy gate electrode over the second dielectric layer; forming a gate spacer surrounding the dummy gate electrode; forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer; forming source/drain regions in the respective LDD regions; removing the dummy gate electrode to form a replacement gate; forming an inter-layer dielectric (ILD) layer over the replacement gate and the source/drain regions; and performing a treatment by introducing a trap-repairing element into at least one of the gate spacer, the second dielectric layer, the surface and the LDD regions at a time before the forming of the source/drain regions or subsequent to the formation of the ILD layer.

公开(公告)号：US20180277678A1

公开(公告)日：2018-09-27

申请号：US15985495

申请日：2018-05-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Hsiung Tsai ,  Kuo-Feng Yu ,  Kei-Wei Chen

IPC: H01L29/78 ,  H01L21/225 ,  H01L21/8238 ,  H01L21/223 ,  H01L29/66 ,  H01L21/324 ,  H01L27/092

Abstract: A semiconductor structure includes a substrate, a first semiconductor fin, a second semiconductor fin, and a first lightly-doped drain (LDD) region. The first semiconductor fin is disposed on the substrate. The first semiconductor fin has a top surface and sidewalls. The second semiconductor fin is disposed on the substrate. The first semiconductor fin and the second semiconductor fin are separated from each other at a nanoscale distance. The first lightly-doped drain (LDD) region is disposed at least in the top surface and the sidewalls of the first semiconductor fin.

公开(公告)号：US20160149017A1

公开(公告)日：2016-05-26

申请号：US14555311

申请日：2014-11-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Kuo-Feng Yu

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/78

CPC classification number: H01L29/4983 ,  H01L21/0206 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/28247 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: Methods and structures for forming devices, such as transistors, are discussed. A method embodiment includes forming a gate spacer along a sidewall of a gate stack on a substrate; passivating at least a portion of an exterior surface of the gate spacer; and epitaxially growing a material in the substrate proximate the gate spacer while the at least the portion of the exterior surface of the gate spacer remains passivated. The passivating can include using at least one of a thermal treatment, a plasma treatment, or a thermal treatment.

Abstract translation: 讨论了用于形成诸如晶体管的器件的方法和结构。 方法实施例包括沿着衬底上的栅极堆叠的侧壁形成栅极间隔物; 钝化栅极隔离物的外表面的至少一部分; 并且在栅极间隔物附近外延生长衬底中的材料，同时栅极间隔物的外表面的至少部分保持钝化。 钝化可以包括使用热处理，等离子体处理或热处理中的至少一种。