公开(公告)号：US20230187535A1

公开(公告)日：2023-06-15

申请号：US17831130

申请日：2022-06-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Jiun Peng ,  Hsuan-Chih Wu ,  Cheng-Chung Chang ,  Shu-Han Chen ,  Hsiu-Hao Tsao ,  Min-Chia Lee ,  Kai-Min Chien ,  Ming-Chang Wen ,  Kuo-Feng Yu ,  Chang-Jhih Syu

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/6656 ,  H01L29/42392 ,  H01L21/823418 ,  H01L21/823468 ,  H01L29/0673 ,  H01L21/823412 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method for manufacturing the semiconductor structure includes forming a fin structure protruding from a substrate, and the fin structure includes first semiconductor material layers and second semiconductor material layers alternately stacked. The method also includes forming a dummy gate structure across the fin structure and forming a gate spacer on a sidewall of the dummy gate structure. The method also includes partially oxidizing the gate spacer to form an oxide layer and removing the oxide layer to form a modified gate spacer. The method also includes removing the first semiconductor material layers to form gaps and forming a gate structure in the gaps to wrap around the second semiconductor material layers and over the second semiconductor material layers to cover the modified gate spacer.

公开(公告)号：US11996468B2

公开(公告)日：2024-05-28

申请号：US17465766

申请日：2021-09-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Chih Lin ,  Hsiu-Hao Tsao ,  Szu-Chi Yang ,  Shih-Hao Lin ,  Yu-Jiun Peng ,  Chang-Jhih Syu ,  An Chyi Wei

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66742 ,  H01L21/02057 ,  H01L21/0259 ,  H01L21/3065 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78696

Abstract: A method of fabricating a device includes providing a fin having an epitaxial layer stack with a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes exposing lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers within a source/drain region of the semiconductor device. In some examples, the method further includes etching the exposed lateral surfaces of the plurality of dummy layers to form recesses and forming an inner spacer within each of the recesses, where the inner spacer includes a sidewall profile having a convex shape. In some cases, and after forming the inner spacer, the method further includes performing a sheet trim process to tune the sidewall profile of the inner spacer such that the convex shape of the sidewall profile becomes a substantially vertical sidewall surface after the sheet trim process.

公开(公告)号：US20240313090A1

公开(公告)日：2024-09-19

申请号：US18674285

申请日：2024-05-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Chih Lin ,  An Chyi Wei ,  Hsiu-Hao Tsao ,  Shih-Hao Lin ,  Szu-Chi Yang ,  Chang-Jhih Syu ,  Yu-Jiun Peng

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66742 ,  H01L21/02057 ,  H01L21/0259 ,  H01L21/3065 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78696

Abstract: A method of fabricating a device includes providing a fin having an epitaxial layer stack with a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes exposing lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers within a source/drain region of the semiconductor device. In some examples, the method further includes etching the exposed lateral surfaces of the plurality of dummy layers to form recesses and forming an inner spacer within each of the recesses, where the inner spacer includes a sidewall profile having a convex shape. In some cases, and after forming the inner spacer, the method further includes performing a sheet trim process to tune the sidewall profile of the inner spacer such that the convex shape of the sidewall profile becomes a substantially vertical sidewall surface after the sheet trim process.