公开(公告)号：US10510756B1

公开(公告)日：2019-12-17

申请号：US16421759

申请日：2019-05-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Yen Tsai ,  Ming-Chi Huang ,  Zoe Chen ,  Wei-Chin Lee ,  Cheng-Lung Hung ,  Da-Yuan Lee ,  Weng Chang ,  Ching-Hwanq Su

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/324 ,  H01L21/027 ,  H01L21/321 ,  H01L29/10 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/768 ,  H01L29/08 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51

Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.

公开(公告)号：US20240243016A1

公开(公告)日：2024-07-18

申请号：US18432251

申请日：2024-02-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Wei Lee ,  Wen-Hung Huang ,  Kuo-Feng Yu ,  Jian-Hao Chen ,  Hsueh-Ju Chen ,  Zoe Chen

IPC: H01L21/8238 ,  H01L21/311 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L21/823857 ,  H01L21/31105 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823821 ,  H01L27/088 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor device includes a first transistor located in a first region of a substrate and a second transistor located in a second region of the substrate. The first transistor includes first channel members vertically stacked above the substrate and a first gate structure wrapping around each of the first channel members. The first gate structure includes a first interfacial layer. The second transistor includes second channel members vertically stacked above the substrate and a second gate structure wrapping around each of the second channel members. The second gate structure includes a second interfacial layer. The second interfacial layer has a first sub-layer and a second sub-layer over the first sub-layer. The first and second sub-layers include different material compositions. A total thickness of the first and second sub-layers is larger than a thickness of the first interfacial layer.

公开(公告)号：US11894276B2

公开(公告)日：2024-02-06

申请号：US17461849

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Wei Lee ,  Wen-Hung Huang ,  Kuo-Feng Yu ,  Jian-Hao Chen ,  Hsueh-Ju Chen ,  Zoe Chen

IPC: H01L21/8238 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/311 ,  H01L27/088

CPC classification number: H01L21/823857 ,  H01L21/31105 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823821 ,  H01L27/088 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: A method includes providing a structure having a first channel member and a second channel member over a substrate. The first channel member is located in a first region of the structure and the second channel member is located in a second region of the structure. The method also includes forming a first oxide layer over the first channel member and a second oxide layer over the second channel member, forming a first dielectric layer over the first oxide layer and a second dielectric layer over the second oxide layer, and forming a capping layer over the second dielectric layer but not over the first dielectric layer. The method further includes performing an annealing process to increase a thickness of the second oxide layer under the capping layer.

公开(公告)号：US20230061018A1

公开(公告)日：2023-03-02

申请号：US17461849

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Wei Lee ,  Wen-Hung Huang ,  Kuo-Feng Yu ,  Jian-Hao Chen ,  Hsueh-Ju Chen ,  Zoe Chen

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/311

Abstract: A method includes providing a structure having a first channel member and a second channel member over a substrate. The first channel member is located in a first region of the structure and the second channel member is located in a second region of the structure. The method also includes forming a first oxide layer over the first channel member and a second oxide layer over the second channel member, forming a first dielectric layer over the first oxide layer and a second dielectric layer over the second oxide layer, and forming a capping layer over the second dielectric layer but not over the first dielectric layer. The method further includes performing an annealing process to increase a thickness of the second oxide layer under the capping layer.

公开(公告)号：US10304835B1

公开(公告)日：2019-05-28

申请号：US15998780

申请日：2018-08-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Yen Tsai ,  Ming-Chi Huang ,  Zoe Chen ,  Wei-Chin Lee ,  Cheng-Lung Hung ,  Da-Yuan Lee ,  Weng Chang ,  Ching-Hwanq Su

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/027 ,  H01L21/321 ,  H01L21/324 ,  H01L21/768 ,  H01L27/092 ,  H01L21/8238

Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.