公开(公告)号：US12068195B2

公开(公告)日：2024-08-20

申请号：US18330466

申请日：2023-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Chieh Wu ,  Tang-Kuei Chang ,  Kuo-Hsiu Wei ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Su-Hao Liu ,  Kuo-Ju Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Ting-Kui Chang ,  Chia Hsuan Lee

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3115 ,  H01L23/485 ,  H01L23/532

CPC classification number: H01L21/76883 ,  H01L21/76825 ,  H01L23/5226 ,  H01L21/31155 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/485 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/00 ,  H01L2924/0002

Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.

公开(公告)号：US12036636B2

公开(公告)日：2024-07-16

申请号：US18174125

申请日：2023-02-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Kung ,  Shang-Yu Wang ,  Ching-Hsiang Tsai ,  Hui-Chi Huang ,  Kei-Wei Chen

IPC: B24B37/10 ,  B24B37/04 ,  B24B37/32 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/768

CPC classification number: B24B37/105 ,  B24B37/042 ,  B24B37/32 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/7684

Abstract: A method of performing a chemical mechanical planarization (CMP) process includes holding a wafer by a retainer ring attached to a carrier, pressing the wafer against a first surface of a polishing pad, the polishing pad rotating at a first speed, dispensing a slurry on the first surface of the polishing pad, and generating vibrations at the polishing pad.

公开(公告)号：US11991936B2

公开(公告)日：2024-05-21

申请号：US18172762

申请日：2023-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Miao Liu ,  Bwo-Ning Chen ,  Kei-Wei Chen

IPC: H10N70/00 ,  H10N70/20

CPC classification number: H10N70/063 ,  H10N70/231 ,  H10N70/253

Abstract: A method of forming a semiconductor device includes patterning a mask layer and a semiconductor material to form a first fin and a second fin with a trench interposing the first fin and the second fin. A first liner layer is formed over the first fin, the second fin, and the trench. An insulation material is formed over the first liner layer. A first anneal is performed, followed by a first planarization of the insulation material to form a first planarized insulation material. After which, a top surface of the first planarized insulation material is over a top surface of the mask layer. A second anneal is performed, followed by a second planarization of the first planarized insulation material to form a second planarized insulation material. The insulation material is etched to form shallow trench isolation (STI) regions, and a gate structure is formed over the semiconductor material.

公开(公告)号：US11951587B2

公开(公告)日：2024-04-09

申请号：US16538464

申请日：2019-08-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Liang Chung ,  Che-Hao Tu ,  Kei-Wei Chen ,  Chih-Wen Liu

IPC: B24B37/005 ,  B24B51/00 ,  H01L21/67

CPC classification number: B24B37/005 ,  B24B51/00 ,  H01L21/67253

Abstract: The present disclosure is directed to techniques of zone-based target control in chemical mechanical polishing of wafers. Multiple zones are identified on a surface of a wafer. The CMP target is achieved on each zone in a sequence of CMP processes. Each CMP process in the sequence achieves the CMP target for only one zone, using a CMP process selective to other zones.

公开(公告)号：US11854901B2

公开(公告)日：2023-12-26

申请号：US17843694

申请日：2022-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsiung Yen ,  Ta-Chun Ma ,  Chien-Chang Su ,  Jung-Jen Chen ,  Pei-Ren Jeng ,  Chii-Horng Li ,  Kei-Wei Chen

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/165 ,  H01L29/10 ,  H01L21/02 ,  H01L21/324 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/0206 ,  H01L21/0217 ,  H01L21/02068 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02532 ,  H01L21/324 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/1037 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: A device is manufactured by providing a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.

公开(公告)号：US11854872B2

公开(公告)日：2023-12-26

申请号：US17869560

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Kung ,  Chih-Chieh Chang ,  Kao-Feng Liao ,  Hui-Chi Huang ,  Kei-Wei Chen

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/76831 ,  H01L21/7684 ,  H01L21/76814 ,  H01L21/76877 ,  H01L21/02211 ,  H01L21/76843 ,  H01L29/66795

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.

公开(公告)号：US11569387B2

公开(公告)日：2023-01-31

申请号：US17188779

申请日：2021-03-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun Hsiung Tsai ,  Kei-Wei Chen

IPC: H01L29/78 ,  H01L21/306 ,  H01L21/265 ,  H01L29/66 ,  H01L29/267 ,  H01L29/165

Abstract: A semiconductor Fin FET device includes a fin structure disposed over a substrate. The fin structure includes a channel layer. The Fin FET device also includes a gate structure including a gate electrode layer and a gate dielectric layer, covering a portion of the fin structure. Side-wall insulating layers are disposed over both main sides of the gate electrode layer. The Fin FET device includes a source and a drain, each including a stressor layer disposed in a recess formed by removing the fin structure not covered by the gate structure. The stressor layer includes a first to a third stressor layer formed in this order. In the source, an interface between the first stressor layer and the channel layer is located under one of the side-wall insulating layers closer to the source or the gate electrode.

公开(公告)号：US11551936B2

公开(公告)日：2023-01-10

申请号：US16513664

申请日：2019-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Kung ,  Hui-Chi Huang ,  Kei-Wei Chen ,  Yen-Ting Chen

IPC: H01L21/306 ,  B24B37/24 ,  H01L21/321

Abstract: Provided herein are polishing pads in which microcapsules that include a polymer material and are dispersed, as well as methods of making and using the same. Such microcapsules are configured to break open (e.g., when the polishing pad is damaged during the dressing process), which releases the polymer material. When contacted with ultraviolet light the polymer material at least partially cures, healing the damage to the polishing pad. Such polishing pads have a longer lifetime and a more stable remove rate when compared to standard polishing pads.

公开(公告)号：US20220382947A1

公开(公告)日：2022-12-01

申请号：US17814991

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Shuo Liu ,  Chih-Chun Hsia ,  Hsin-Ting Chou ,  Kuanhua Su ,  William Weilun Hong ,  Chih Hung Chen ,  Kei-Wei Chen

IPC: G06F30/392 ,  G06T7/00

Abstract: A method includes cropping a plurality of images from a layout of an integrated circuit, generating a first plurality of hash values, each from one of the plurality of images, loading a second plurality of hash values stored in a hotspot library, and comparing each of the first plurality of hash values with each of the second plurality of hash values. The step of comparing includes calculating a similarity value between the each of the first plurality of hash values and the each of the second plurality of hash values. The method further includes comparing the similarity value with a pre-determined threshold similarity value, and in response to a result that the similarity value is greater than the pre-determined threshold similarity value, recording a position of a corresponding image that has the result. The position is the position of the corresponding image in the layout.

公开(公告)号：US20220122884A1

公开(公告)日：2022-04-21

申请号：US17646024

申请日：2021-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Chieh Wu ,  Tang-Kuei Chang ,  Kuo-Hsiu Wei ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Su-Hao Liu ,  Kuo-Ju Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Ting-Kui Chang ,  Chia Hsuan Lee

IPC: H01L21/768 ,  H01L23/522

Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.