公开(公告)号：US20240355826A1

公开(公告)日：2024-10-24

申请号：US18760800

申请日：2024-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Chi Tai ,  Yi-Fang Pai ,  Tsz-Mei Kwok ,  Tsung-Hsi Yang ,  Jeng-Wei Yu ,  Cheng-Hsiung Yen ,  Jui-Hsuan Chen ,  Chii-Horng Li ,  Yee-Chia Yeo ,  Heng-Wen Ting ,  Ming-Hua Yu

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.

公开(公告)号：US20220328358A1

公开(公告)日：2022-10-13

申请号：US17843694

申请日：2022-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsiung Yen ,  Ta-Chun Ma ,  Chien-Chang Su ,  Jung-Jen Chen ,  Pei-Ren Jeng ,  Chii-Horng Li ,  Kei-Wei Chen

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/165 ,  H01L29/10 ,  H01L21/02 ,  H01L21/324 ,  H01L27/092

Abstract: A device is manufactured by providing a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.

公开(公告)号：US20210366715A1

公开(公告)日：2021-11-25

申请号：US17396948

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Ma ,  Yi-Cheng Li ,  Pin-Ju Liang ,  Cheng-Po Chau ,  Jung-Jen Chen ,  Pei-Ren Jeng ,  Chii-Horng Li ,  Kei-Wei Chen ,  Cheng-Hsiung Yen

IPC: H01L21/223 ,  H01L29/66 ,  H01L21/311 ,  H01L21/324 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092

Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate, the substrate including silicon, the first fin including silicon germanium; forming an isolation region around the first fin, an oxide layer being formed on the first fin during formation of the isolation region; removing the oxide layer from the first fin with a hydrogen-based etching process, silicon at a surface of the first fin being terminated with hydrogen after the hydrogen-based etching process; desorbing the hydrogen from the silicon at the surface of the first fin to depassivate the silicon; and exchanging the depassivated silicon at the surface of the first fin with germanium at a subsurface of the first fin.

公开(公告)号：US20210098308A1

公开(公告)日：2021-04-01

申请号：US17121490

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsiung Yen ,  Ta-Chun Ma ,  Chien-Chang Su ,  Jung-Jen Chen ,  Pei-Ren Jeng ,  Chii-Horng Li ,  Kei-Wei Chen

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/165 ,  H01L29/10 ,  H01L21/02 ,  H01L21/324 ,  H01L27/092

Abstract: A device is manufactured by providing a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.

公开(公告)号：US11854901B2

公开(公告)日：2023-12-26

申请号：US17843694

申请日：2022-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsiung Yen ,  Ta-Chun Ma ,  Chien-Chang Su ,  Jung-Jen Chen ,  Pei-Ren Jeng ,  Chii-Horng Li ,  Kei-Wei Chen

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/165 ,  H01L29/10 ,  H01L21/02 ,  H01L21/324 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/0206 ,  H01L21/0217 ,  H01L21/02068 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02532 ,  H01L21/324 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/1037 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: A device is manufactured by providing a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.

公开(公告)号：US11652105B2

公开(公告)日：2023-05-16

申请号：US17143681

申请日：2021-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Chi Tai ,  Yi-Fang Pai ,  Tsz-Mei Kwok ,  Tsung-Hsi Yang ,  Jeng-Wei Yu ,  Cheng-Hsiung Yen ,  Jui-Hsuan Chen ,  Chii-Horng Li ,  Yee-Chia Yeo ,  Heng-Wen Ting ,  Ming-Hua Yu

IPC: H01L29/76 ,  H01L29/94 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.

公开(公告)号：US12057450B2

公开(公告)日：2024-08-06

申请号：US17818627

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Chi Tai ,  Yi-Fang Pai ,  Tsz-Mei Kwok ,  Tsung-Hsi Yang ,  Jeng-Wei Yu ,  Cheng-Hsiung Yen ,  Jui-Hsuan Chen ,  Chii-Horng Li ,  Yee-Chia Yeo ,  Heng-Wen Ting ,  Ming-Hua Yu

IPC: H01L29/94 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/76 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.

公开(公告)号：US20220384437A1

公开(公告)日：2022-12-01

申请号：US17818627

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Chi Tai ,  Yi-Fang Pai ,  Tsz-Mei Kwok ,  Tsung-Hsi Yang ,  Jeng-Wei Yu ,  Cheng-Hsiung Yen ,  Jui-Hsuan Chen ,  Chii-Horng Li ,  Yee-Chia Yeo ,  Heng-Wen Ting ,  Ming-Hua Yu

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.

公开(公告)号：US11367660B2

公开(公告)日：2022-06-21

申请号：US17121490

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsiung Yen ,  Ta-Chun Ma ,  Chien-Chang Su ,  Jung-Jen Chen ,  Pei-Ren Jeng ,  Chii-Horng Li ,  Kei-Wei Chen

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/165 ,  H01L29/10 ,  H01L21/02 ,  H01L21/324 ,  H01L27/092

Abstract: A device is manufactured by providing a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.

公开(公告)号：US20220028856A1

公开(公告)日：2022-01-27

申请号：US17143681

申请日：2021-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Chi Tai ,  Yi-Fang Pai ,  Tsz-Mei Kwok ,  Tsung-Hsi Yang ,  Jeng-Wei Yu ,  Cheng-Hsiung Yen ,  Jui-Hsuan Chen ,  Chii-Horng Li ,  Yee-Chia Yeo ,  Heng-Wen Ting ,  Ming-Hua Yu

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66

Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.