Nanosheet FETs with stacked nanosheets having smaller horizontal spacing than vertical spacing for large effective width
    42.
    发明授权
    Nanosheet FETs with stacked nanosheets having smaller horizontal spacing than vertical spacing for large effective width 有权
    具有堆叠的纳米片的纳米片FET具有比垂直间隔更小的水平间距,用于较大的有效宽度

    公开(公告)号:US09490323B2

    公开(公告)日:2016-11-08

    申请号:US14722402

    申请日:2015-05-27

    Abstract: A device including a stacked nanosheet field effect transistor (FET) may include a substrate, a first channel pattern on the substrate, a second channel pattern on the first channel pattern, a gate that is configured to surround portions of the first channel pattern and portions of the second channel pattern, and source/drain regions on opposing ends of the first channel pattern and second channel pattern. The first and second channel patterns may each include a respective plurality of nanosheets arranged in a respective horizontal plane that is parallel to a surface of the substrate. The nanosheets may be spaced apart from each other at a horizontal spacing distance between adjacent ones of the nanosheets. The second channel pattern may be spaced apart from the first channel pattern at a vertical spacing distance from the first channel pattern to the second channel pattern that is greater than the horizontal spacing distance.

    Abstract translation: 包括堆叠的纳米片场效应晶体管(FET)的器件可以包括衬底,衬底上的第一沟道图案,第一沟道图案上的第二沟道图案,被配置为围绕第一沟道图案的部分的栅极和部分 的第二沟道图案和第一沟道图案和第二沟道图案的相对端上的源极/漏极区域。 第一和第二通道图案可以各自包括布置在平行于基板的表面的相应水平平面中的相应的多个纳米片。 纳米片可以在相邻的纳米片之间的水平间隔距离处彼此间隔开。 第二通道图案可以与第一通道图案间隔开距离第一通道图案到第二通道图案的垂直间隔距离大于水平间隔距离。

    Semiconductor device and method of forming the same
    43.
    发明授权
    Semiconductor device and method of forming the same 有权
    半导体器件及其形成方法

    公开(公告)号:US09490263B2

    公开(公告)日:2016-11-08

    申请号:US14312702

    申请日:2014-06-24

    Abstract: A semiconductor device includes a substrate on which a plurality of logic cells are provided, and a plurality of active portions provided on the substrate and extending in a first direction. Contacts and gate structures extend in a second direction intersecting the first direction and are alternately arranged. A common conductive line extends along a boundary region of the plurality of logic cells in the first direction. At least one of the contacts is electrically connected to the common conductive line through a via therebetween, and each of the contacts intersects a plurality of the active portions. End portions of the contacts are aligned with each other along the first direction.

    Abstract translation: 半导体器件包括其上设置有多个逻辑单元的基板和设置在基板上并沿第一方向延伸的多个有源部分。 触点和栅极结构在与第一方向相交的第二方向上延伸并且交替地布置。 公共导线沿第一方向沿多个逻辑单元的边界区域延伸。 至少一个触点通过它们之间的通孔电连接到公共导线,并且每个触点与多个有源部分相交。 触点的端部沿着第一方向彼此对准。

    Multiple Channel Length Finfets with Same Physical Gate Length
    44.
    发明申请
    Multiple Channel Length Finfets with Same Physical Gate Length 有权
    具有相同物理栅极长度的多通道长度Finfets

    公开(公告)号:US20150318282A1

    公开(公告)日:2015-11-05

    申请号:US14683926

    申请日:2015-04-10

    Abstract: A semiconductor structure includes a first finFET device including a first fin, a first gate electrode structure on sidewalls and an upper surface of the first fin, a first channel region beneath the first gate electrode structure, and first source and drain regions in the first fin on opposite sides of the first channel region, and a second finFET device including a second fin, a second gate electrode structure on sidewalls and an upper surface of the second fin, a second channel region beneath the second gate electrode structure, and second source and drain regions in the second fin on opposite sides of the second channel region. The second gate electrode structure has a second physical gate length that is substantially the same as a first physical gate length of the first gate electrode structure, and the second finFET device has a second effective channel length that is different from a first effective channel length of the first gate electrode structure.

    Abstract translation: 半导体结构包括第一鳍式FET器件,其包括第一鳍片,侧壁上的第一栅极电极结构和第一鳍片的上表面,第一栅电极结构下方的第一沟道区域,第一鳍片中的第一源极和漏极区域 在第一沟道区域的相对侧上,以及第二鳍状FET器件,其包括第二鳍片,侧壁上的第二栅电极结构和第二鳍片的上表面,第二栅电极结构下方的第二沟道区域,以及第二源极和 第二鳍片的漏极区域在第二沟道区域的相对侧上。 第二栅极电极结构具有与第一栅极电极结构的第一物理栅极长度基本相同的第二物理栅极长度,并且第二finFET器件具有与第一栅极电极结构的第一有效沟道长度不同的第二有效沟道长度 第一栅电极结构。

    Semiconductor device and method for making the same

    公开(公告)号:US10811415B2

    公开(公告)日:2020-10-20

    申请号:US16298887

    申请日:2019-03-11

    Abstract: According to some example embodiments of the present disclosure, a semiconductor device includes: a substrate; a first semiconductor layer over the substrate, the first semiconductor layer being a first type of semiconductor device; and a second semiconductor layer over the substrate and the first semiconductor layer, the second semiconductor layer being the first type of semiconductor device, wherein a first portion of the first semiconductor layer overlaps the second semiconductor layer when viewed in a direction perpendicular to a plane of the substrate and a second portion of the first semiconductor layer is laterally offset from the second semiconductor layer when viewed in the direction perpendicular to the plane of the substrate.

    NANOSHEET FIELD EFFECT TRANSISTOR CELL ARCHITECTURE

    公开(公告)号:US20200152801A1

    公开(公告)日:2020-05-14

    申请号:US16390859

    申请日:2019-04-22

    Abstract: A semiconductor device includes first and second GAA FETs spaced apart by an inter-channel spacing. Each of the GAA FETs includes a horizontal nanosheet conductive channel structure, a gate material completely surrounding the horizontal nanosheet conductive channel structure, source and drain regions at opposite ends of the horizontal nanosheet conductive channel structure, source and drain contacts on the source and drain regions. A width of the horizontal nanosheet conductive channel structure of the first GAA FET or the second GAA FET is smaller than a maximum allowed width. The semiconductor device also includes a gate contact on the gate material in the inter-channel spacing between the first and second GAA FETs. The gate contact is spaced apart by a distance from each of the source and drain regions of the first and second GAA FETs in a range from a minimum design rule spacing to a maximum distance.

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