Abstract:
Provided is a semiconductor device including a substrate with a plurality of logic cells, transistors provided in the plurality of logic cells, contact plugs connected to electrodes of the transistors, first via plugs in contact with top surfaces of the contact plugs, and first wires in contact with top surfaces of the first via plugs. The first wires may include a common conductive line connected to the plurality of logic cells through the contact plugs, and all of the first wires may be shaped like a straight line extending parallel to a specific direction.
Abstract:
A device including a stacked nanosheet field effect transistor (FET) may include a substrate, a first channel pattern on the substrate, a second channel pattern on the first channel pattern, a gate that is configured to surround portions of the first channel pattern and portions of the second channel pattern, and source/drain regions on opposing ends of the first channel pattern and second channel pattern. The first and second channel patterns may each include a respective plurality of nanosheets arranged in a respective horizontal plane that is parallel to a surface of the substrate. The nanosheets may be spaced apart from each other at a horizontal spacing distance between adjacent ones of the nanosheets. The second channel pattern may be spaced apart from the first channel pattern at a vertical spacing distance from the first channel pattern to the second channel pattern that is greater than the horizontal spacing distance.
Abstract:
A semiconductor device includes a substrate on which a plurality of logic cells are provided, and a plurality of active portions provided on the substrate and extending in a first direction. Contacts and gate structures extend in a second direction intersecting the first direction and are alternately arranged. A common conductive line extends along a boundary region of the plurality of logic cells in the first direction. At least one of the contacts is electrically connected to the common conductive line through a via therebetween, and each of the contacts intersects a plurality of the active portions. End portions of the contacts are aligned with each other along the first direction.
Abstract:
A semiconductor structure includes a first finFET device including a first fin, a first gate electrode structure on sidewalls and an upper surface of the first fin, a first channel region beneath the first gate electrode structure, and first source and drain regions in the first fin on opposite sides of the first channel region, and a second finFET device including a second fin, a second gate electrode structure on sidewalls and an upper surface of the second fin, a second channel region beneath the second gate electrode structure, and second source and drain regions in the second fin on opposite sides of the second channel region. The second gate electrode structure has a second physical gate length that is substantially the same as a first physical gate length of the first gate electrode structure, and the second finFET device has a second effective channel length that is different from a first effective channel length of the first gate electrode structure.
Abstract:
A semiconductor cell block includes a series of layers arranged in a stack. The layers include one or more first layers each having a first height and one or more second layers each having a second height. The second height is larger than the first height, and the second height is a non-integer multiple of the first height. The semiconductor cell block also includes a first semiconductor logic cell having a first cell height in one of the series of layers, and a second semiconductor logic cell having a second cell height in one of the series of layers. The second cell height is larger than the first cell height, and the second cell height is a non-integer value multiple of the first cell height.
Abstract:
A weight cell and device are herein disclosed. The weight cell includes a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET, a second FET and a second resistive memory element connected to a drain of the second FET, the drain of the first FET is connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET, and a third FET, and a load resistor connected to a drain of the third FET.
Abstract:
According to some example embodiments of the present disclosure, a semiconductor device includes: a substrate; a first semiconductor layer over the substrate, the first semiconductor layer being a first type of semiconductor device; and a second semiconductor layer over the substrate and the first semiconductor layer, the second semiconductor layer being the first type of semiconductor device, wherein a first portion of the first semiconductor layer overlaps the second semiconductor layer when viewed in a direction perpendicular to a plane of the substrate and a second portion of the first semiconductor layer is laterally offset from the second semiconductor layer when viewed in the direction perpendicular to the plane of the substrate.
Abstract:
A semiconductor integrated circuit including a substrate, a series of metal layers, and a series of insulating layers. The metal layers and the insulating layers are alternately arranged in a stack on the substrate. The semiconductor integrated circuit also includes at least two standard cells in the substrate and at least one power rail crossing over boundaries of the at least two standard cells. The power rail includes a vertical section of conductive material extending continuously through at least two vertical levels of the stack. The two vertical levels of the stack include one metal layer and one insulating layer. The insulating layer is above the metal layer.
Abstract:
A semiconductor device includes first and second GAA FETs spaced apart by an inter-channel spacing. Each of the GAA FETs includes a horizontal nanosheet conductive channel structure, a gate material completely surrounding the horizontal nanosheet conductive channel structure, source and drain regions at opposite ends of the horizontal nanosheet conductive channel structure, source and drain contacts on the source and drain regions. A width of the horizontal nanosheet conductive channel structure of the first GAA FET or the second GAA FET is smaller than a maximum allowed width. The semiconductor device also includes a gate contact on the gate material in the inter-channel spacing between the first and second GAA FETs. The gate contact is spaced apart by a distance from each of the source and drain regions of the first and second GAA FETs in a range from a minimum design rule spacing to a maximum distance.
Abstract:
An integrated circuit (IC) including a circuit block including a plurality of complementary metal oxide semiconductor field-effect transistors (CMOSFETs), and a tunnel field-effect transistor (TFET) between the circuit block and ground for power gating the circuit block.