公开(公告)号：US20150227673A1

公开(公告)日：2015-08-13

申请号：US14533553

申请日：2014-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Jong Lee ,  Chul-Hong Park ,  Roo-Li Choi ,  Duck-Hyung Hur

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F1/70 ,  H01L21/027

Abstract: A design rule generating method is provided. The method includes receiving a test pattern, providing a plurality of workflows, which correspond to the test pattern and are preset in relation to a lithography model and a mask generation method, and performing simulation on the test pattern according to a workflow selected from the workflows.

Abstract translation: 提供了一种设计规则生成方法。 该方法包括接收测试图案，提供对应于测试图案并相对于光刻模型和掩模生成方法预设的多个工作流程，以及根据从工作流程中选择的工作流程在测试图案上执行模拟 。

公开(公告)号：US09230053B2

公开(公告)日：2016-01-05

申请号：US14533553

申请日：2014-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Jong Lee ,  Chul-Hong Park ,  Roo-Li Choi ,  Duck-Hyung Hur

IPC: G06F17/50 ,  H01L21/027

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F1/70 ,  H01L21/027

Abstract: A design rule generating method is provided. The method includes receiving a test pattern, providing a plurality of workflows, which correspond to the test pattern and are preset in relation to a lithography model and a mask generation method, and performing simulation on the test pattern according to a workflow selected from the workflows.

Abstract translation: 提供了一种设计规则生成方法。 该方法包括接收测试图案，提供对应于测试图案并相对于光刻模型和掩模生成方法预设的多个工作流程，以及根据从工作流程中选择的工作流程在测试图案上执行模拟 。

公开(公告)号：US09490263B2

公开(公告)日：2016-11-08

申请号：US14312702

申请日：2014-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sooyeon Jeon ,  Rwik Sengupta ,  Chulhong Park ,  Kwanyoung Chun ,  Yusun Lee ,  Hyun-Jong Lee

IPC: H01L27/118 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L2027/11861 ,  H01L2027/11881

Abstract: A semiconductor device includes a substrate on which a plurality of logic cells are provided, and a plurality of active portions provided on the substrate and extending in a first direction. Contacts and gate structures extend in a second direction intersecting the first direction and are alternately arranged. A common conductive line extends along a boundary region of the plurality of logic cells in the first direction. At least one of the contacts is electrically connected to the common conductive line through a via therebetween, and each of the contacts intersects a plurality of the active portions. End portions of the contacts are aligned with each other along the first direction.

Abstract translation: 半导体器件包括其上设置有多个逻辑单元的基板和设置在基板上并沿第一方向延伸的多个有源部分。 触点和栅极结构在与第一方向相交的第二方向上延伸并且交替地布置。 公共导线沿第一方向沿多个逻辑单元的边界区域延伸。 至少一个触点通过它们之间的通孔电连接到公共导线，并且每个触点与多个有源部分相交。 触点的端部沿着第一方向彼此对准。

公开(公告)号：US09141751B2

公开(公告)日：2015-09-22

申请号：US13950799

申请日：2013-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Jong Lee ,  Soo-Han Choi ,  Jung-Ho Do ,  Chul-Hong Park ,  Sang-Pil Sim

IPC: G06F17/50 ,  H01L21/308

CPC classification number: G06F17/5081 ,  H01L21/3086

Abstract: A method of forming a pattern includes defining a plurality of patterns, defining a plurality of pitch violating patterns that contact the plurality of patterns and correspond to regions between the patterns, classifying the plurality of pitch violating patterns into a first region and a second region that is adjacent to the first region, selecting one of the first region and the second region, and forming an initial pattern defined as the selected first or second region. The selecting includes performing at least one of i) selecting a region that contact dummy patterns, ii) selecting a region of a same kind as one region, and iii) selecting a region that contacts a concave part of an enclosure from the first region and the second region.

Abstract translation: 形成图案的方法包括限定多个图案，限定接触所述多个图案并对应于所述图案之间的区域的多个倾斜违规图案，将所述多个音高违规图案分类为第一区域和第二区域， 与第一区域相邻，选择第一区域和第二区域中的一个，以及形成被定义为所选择的第一或第二区域的初始图案。 所述选择包括执行以下各项中的至少一个：i）选择接触虚拟图案的区域，ii）选择与一个区域相同类型的区域，以及iii）从所述第一区域选择与外壳的凹部接触的区域，以及 第二个地区。