公开(公告)号：US09589619B2

公开(公告)日：2017-03-07

申请号：US14617919

申请日：2015-02-09

Applicant: QUALCOMM Incorporated

Inventor： Kangho Lee ,  Jimmy Kan ,  Seung Hyuk Kang

IPC: G11C11/00 ,  G11C11/16 ,  G11C11/18 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  G11C8/00

CPC classification number: G11C11/1675 ,  G11C8/005 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/18 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Methods and apparatus relating to spin-orbit-torque magnetoresistive random access memory with voltage-controlled anisotropy are disclosed. In an example, disclosed is a three-terminal magnetic tunnel junction (MTJ) storage element that is programmed via a combination of voltage-controlled magnetic anisotropy (VCMA) and spin-orbit torque (SOT) techniques. Also disclosed is a memory controller configured to program the three-terminal MTJ storage element via VCMA and SOT techniques. The disclosed devices improve efficiency over conventional devices by using less write energy, while having a design that is simpler and more scalable than conventional devices. The disclosed devices also have increased thermal stability without increasing required switching current, as critical switching current between states is essentially the same.

Abstract translation: 公开了具有电压控制各向异性的自旋轨道转矩磁阻随机存取存储器的方法和装置。 在一个实例中，公开了通过压控磁各向异性（VCMA）和自旋 - 轨道转矩（SOT）技术的组合来编程的三端磁隧道结（MTJ）存储元件。 还公开了一种被配置为经由VCMA和SOT技术对三端MTJ存储元件进行编程的存储器控​​制器。 所公开的设备通过使用较少的写入能量来提高与传统设备的效率，同时具有比常规设备更简单和更可扩展的设计。 所公开的装置还具有增加的热稳定性，而不增加所需的开关电流，因为状态之间的关键开关电流基本相同。

公开(公告)号：US09548333B2

公开(公告)日：2017-01-17

申请号：US14496525

申请日：2014-09-25

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Xia Li ,  Seung Hyuk Kang

IPC: H01L27/22 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L45/02 ,  H01L45/00 ,  H01L43/08 ,  H01L43/12

CPC classification number: H01L27/222 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L43/08 ,  H01L43/12 ,  H01L45/02 ,  H01L45/08 ,  H01L45/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Systems and methods of integration of resistive memory elements with logic elements in advanced nodes with improved mechanical stability and reduced parasitic capacitance include a resistive memory element and a logic element formed in a common integration layer extending between a bottom cap layer and a top cap layer. At least a first intermetal dielectric (IMD) layer of high-K value is formed in the common integration layer and surrounding at least the resistive memory element, to provide high rigidity and mechanical stability. A second IMD layer of low-K value to reduce parasitic capacitance of the logic element is formed in either the common integration layer, a top layer above the top cap layer or an intermediate layer in between the top and bottom cap layers. Air gaps may be formed in one or more IMD layers to further reduce capacitance.

Abstract translation: 电阻式存储器元件与具有改进的机械稳定性和减小的寄生电容的先进节点中的逻辑元件的集成的系统和方法包括形成在底盖层和顶盖层之间延伸的公共集成层中的电阻存储元件和逻辑元件。 至少在公共积分层中形成高K值的第一金属间电介质（IMD）层，并且至少围绕电阻式存储元件，以提供高刚性和机械稳定性。 降低逻辑元件的寄生电容的低K值的第二IMD层形成在公共集成层，顶盖层上的顶层或顶盖层之间的中间层。 可以在一个或多个IMD层中形成气隙，以进一步降低电容。

公开(公告)号：US20160248002A1

公开(公告)日：2016-08-25

申请号：US14630438

申请日：2015-02-24

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Junjing Bao ,  Xia Li ,  Seung Hyuk Kang

IPC: H01L43/02 ,  H01L43/12 ,  G11C11/16 ,  H01L43/08

CPC classification number: H01L43/02 ,  G11C11/16 ,  H01L23/544 ,  H01L43/08 ,  H01L43/12 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: A semiconductor device includes an interconnect layer and a bottom electrode of a resistive memory device. The bottom electrode is coupled to the interconnect layer, and the bottom electrode is comprised of cobalt tungsten phosphorus (CoWP).

Abstract translation: 半导体器件包括电阻式存储器件的互连层和底部电极。 底部电极耦合到互连层，底部电极由钴钨磷（CoWP）组成。

公开(公告)号：US20160246608A1

公开(公告)日：2016-08-25

申请号：US14627318

申请日：2015-02-20

Applicant: QUALCOMM Incorporated

Inventor： Adam Edward Newham ,  Rashid Ahmed Akbar Attar ,  Seung Hyuk Kang ,  Jung Pill Kim ,  Sungryul Kim ,  Taehyun Kim

IPC: G06F9/44 ,  G06F13/28 ,  G06F12/02

CPC classification number: G06F13/28 ,  G06F9/4406 ,  G06F12/0246 ,  G06F2212/7209

Abstract: Multi-step programming of heat-sensitive non-volatile memory (NVM) in processor-based systems, and related methods and systems are disclosed. To avoid relying on programmed instructions stored in heat-sensitive NVM during fabrication, wherein the programmed instructions can become corrupted during thermal packaging processes, the NVM is programmed in a multi-step programming process. In a first programming step, a boot loader comprising programming instructions is loaded into the NVM. The boot loader may be loaded into the NVM after the thermal processes during packaging are completed to avoid risking data corruption in the boot loader. Thereafter, the programmed image can be loaded quickly into a NV program memory over the peripheral interface using the boot loader to save programming time and associated costs, as opposed to loading the programmed image using lower transfer rate programming techniques. The processor can execute the program instructions to carry out tasks in the processor-based system.

Abstract translation: 公开了基于处理器的系统中的热敏非易失性存储器（NVM）的多步编程以及相关的方法和系统。 为了避免在制造期间依赖于存储在热敏NVM中的编程指令，其中编程指令可能在热封装过程中被破坏，NVM以多步编程过程编程。 在第一编程步骤中，包括编程指令的引导加载器被加载到NVM中。 引导加载程序可能在打包完成后的热处理后加载到NVM中，以避免引导加载程序中的数据损坏风险。 此后，与使用较低传输速率编程技术加载编程图像相比，编程图像可以使用引导加载程序通过外设接口快速加载到NV程序存储器中，从而节省编程时间和相关成本。 处理器可以执行程序指令以在基于处理器的系统中执行任务。

公开(公告)号：US09406689B2

公开(公告)日：2016-08-02

申请号：US14044725

申请日：2013-10-02

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Seung Hyuk Kang

IPC: H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/7883 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/11517 ,  H01L27/11551 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/788 ,  H01L29/7881

Abstract: A method for fabricating a multiple time programmable (MTP) device includes forming fins of a first conducting type on a substrate of a second conducting type. The method further includes forming a floating gate dielectric to partially surround the fins. The method also includes forming a floating gate on the floating gate dielectric. The method also includes forming a coupling film on the floating gate and forming a coupling gate on the coupling film.

Abstract translation: 一种制造多时间可编程（MTP）器件的方法包括在第二导电类型的衬底上形成第一导电类型的鳍片。 该方法还包括形成浮动栅极电介质以部分地围绕鳍片。 该方法还包括在浮栅电介质上形成浮栅。 该方法还包括在浮栅上形成耦合膜并在耦合膜上形成耦合栅极。

公开(公告)号：US09318696B2

公开(公告)日：2016-04-19

申请号：US14195566

申请日：2014-03-03

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Xia Li ,  Seung Hyuk Kang ,  Shiqun Gu

IPC: H01L21/00 ,  H01L43/12 ,  H01L43/08 ,  H01L43/02 ,  H01L27/22

CPC classification number: H01L43/12 ,  H01L21/76802 ,  H01L21/76813 ,  H01L21/76832 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: Systems and methods for forming precise and self-aligned top metal contact for a Magnetoresistive random-access memory (MRAM) device include forming a magnetic tunnel junction (MTJ) in a common interlayer metal dielectric (IMD) layer with a logic element. A low dielectric constant (K) etch stop layer is selectively retained over an exposed top surface of the MTJ. Etching is selectively performed through a top IMD layer formed over the low K etch stop layer and the common IMD layer, based on a first chemistry which prevents etching through the low K etch stop layer. By switching chemistry to a second chemistry which precisely etches through the low K etch stop layer, an opening is created for forming a self-aligned top contact to the exposed top surface of the MTJ.

Abstract translation: 用于形成用于磁阻随机存取存储器（MRAM）器件的精确和自对准的顶部金属接触的系统和方法包括在具有逻辑元件的公共层间金属电介质（IMD）层中形成磁性隧道结（MTJ）。 低介电常数（K）蚀刻停止层选择性地保留在MTJ的暴露的顶表面上。 基于防止蚀刻通过低K蚀刻停止层的第一化学反应，通过形成在低K蚀刻停止层和公共IMD层上的顶部IMD层选择性地进行蚀刻。 通过将化学转换成精确地蚀刻通过低K蚀刻停止层的第二化学物质，形成一个开口以形成与MTJ暴露的顶表面的自对准顶部接触。

公开(公告)号：US20150340101A1

公开(公告)日：2015-11-26

申请号：US14820101

申请日：2015-08-06

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung Hyuk Kang ,  Xiaochun Zhu

IPC: G11C17/08

CPC classification number: G11C17/08 ,  G11C7/00 ,  G11C7/12 ,  G11C11/40 ,  G11C11/404 ,  G11C17/16 ,  G11C2211/4016 ,  H01L27/105 ,  H01L27/10802 ,  H01L29/7841

Abstract: A method includes applying a programming voltage to a drain of an access transistor, where a source of the access transistor is coupled to a drain region of a one-time programmable (OTP) device. The method also includes applying a first voltage to a gate of the OTP device and a second voltage to a terminal of the OTP device to bias a channel region of the OTP device, where the first voltage and the second voltage are substantially equal.

Abstract translation: 一种方法包括将编程电压施加到存取晶体管的漏极，其中存取晶体管的源极耦合到一次可编程（OTP）器件的漏极区。 该方法还包括将第一电压施加到OTP器件的栅极，并将第二电压施加到OTP器件的端子以偏置OTP器件的沟道区域，其中第一电压和第二电压基本相等。

公开(公告)号：US09135976B2

公开(公告)日：2015-09-15

申请号：US14104443

申请日：2013-12-12

Applicant: QUALCOMM Incorporated

Inventor： Wenqing Wu ,  Kendrick Hoy Leong Yuen ,  Xiaochun Zhu ,  Seung Hyuk Kang ,  Matthew Michael Nowak ,  Jeffrey Alexander Levin ,  Robert P. Gilmore ,  Nicholas Ka Ming Yu

IPC: G11C11/00 ,  G11C11/16 ,  G11C11/56 ,  G11C11/54

CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/54 ,  G11C11/5607

Abstract: A probabilistic programming current is injected into a cluster of bi-stable probabilistic switching elements, the probabilistic programming current having parameters set to result in a less than unity probability of any given bi-stable switching element switching, and a resistance of the cluster of bi-stable switching elements is detected. The probabilistic programming current is injected and the resistance of the cluster state detected until a termination condition is met. Optionally the termination condition is detecting the resistance of the cluster of bi-stable switching elements at a value representing a multi-bit data.

Abstract translation: 将概率编程电流注入到双稳定概率开关元件簇中，概率编程电流具有设置为导致任何给定双稳态开关元件切换的小于一概率的参数，以及bi的簇的电阻 - 检测到稳定的开关元件。 注入概率编程电流，并检测到簇状态的电阻，直到满足终止条件。 可选地，终止条件是以表示多位数据的值检测双稳态开关元件群的电阻。

公开(公告)号：US08969984B2

公开(公告)日：2015-03-03

申请号：US14048704

申请日：2013-10-08

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Seung Hyuk Kang ,  Xia Li ,  Kangho Lee

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L43/10 ,  H01L27/22

CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A magnetic tunnel junction device includes a Synthetic Anti-Ferromagnetic (SAF) layer, a first free layer, and second free layer. The magnetic tunnel junction device further includes a spacer layer between the first and second free layers. The first free layer is magneto-statically coupled to the second free layer. A thickness of the spacer layer is at least 4 Angstroms.

Abstract translation: 磁性隧道结装置包括合成反铁磁（SAF）层，第一自由层和第二自由层。 磁性隧道结装置还包括在第一和第二自由层之间的间隔层。 第一自由层被磁静态耦合到第二自由层。 间隔层的厚度至少为4埃。

公开(公告)号：US20150056722A1

公开(公告)日：2015-02-26

申请号：US14518459

申请日：2014-10-20

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung Hyuk Kang ,  Matthew Michael Nowak

IPC: H01L43/12

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/08

Abstract: A memory device may comprise a magnetic tunnel junction (MTJ) stack, a bottom electrode (BE) layer, and a contact layer. The MTJ stack may include a free layer, a barrier, and a pinned layer. The BE layer may be coupled to the MTJ stack, and encapsulated in a planarized layer. The BE layer may also have a substantial common axis with the MTJ stack. The contact layer may be embedded in the BE layer, and form an interface between the BE layer and the MTJ stack.

Abstract translation: 存储器件可以包括磁性隧道结（MTJ）堆叠，底部电极（BE）层和接触层。 MTJ堆叠可以包括自由层，阻挡层和钉扎层。 BE层可以耦合到MTJ堆叠，并且封装在平坦化层中。 BE层也可以具有与MTJ叠层相当的共同轴。 接触层可以嵌入在BE层中，并且在BE层和MTJ堆叠之间形成界面。