公开(公告)号：US20170301770A1

公开(公告)日：2017-10-19

申请号：US15633934

申请日：2017-06-27

Applicant: International Business Machines Corporation

Inventor： Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Juntao Li ,  Fee Li Lie ,  Stuart A. Sieg ,  John R. Sporre

IPC: H01L29/66 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L29/6681 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0657 ,  H01L29/42356 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/785

Abstract: Embodiments of the present invention provide a structure and method of minimizing stress relaxation during fin formation. Embodiments may involve forming a looped spacer on an upper surface of a substrate and adjacent to at least a sidewall of a mandrel. The mandrel may be removed, leaving the looped spacer on the substrate. An exposed portion of the substrate may be removed to form a looped fin below the looped spacer. The spacer may be removed, leaving a looped fin. A looped fin formation may reduce stress relaxation compared to conventional fin formation methods. Embodiments may include forming a gate over a looped portion of a looped fin. Securing a looped portion in position with a gate may decrease stress relaxation in the fin. Thus, a looped fin with a looped portion of the looped fin under a gate may have substantially reduced stress relaxation compared to a conventional fin.

公开(公告)号：US20170054002A1

公开(公告)日：2017-02-23

申请号：US14830969

申请日：2015-08-20

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie ,  Stuart A. Sieg

IPC: H01L29/66

CPC classification number: H01L21/845 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/76213 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.

Abstract translation: 一种用于在衬底上形成翅片的方法包括图案化和蚀刻第一半导体材料的层以限定应变翅片，在鳍片上沉积第二半导体材料层，第二半导体材料可操作以将应变保持在 应变翅片，蚀刻以去除第二半导体材料的一部分以限定暴露鳍片的一部分的腔，蚀刻以去除鳍的暴露部分，使得鳍分成第一段和第二段，以及 在空腔中沉积绝缘体材料，绝缘体材料接触翅片的第一段和翅片的第二段。

公开(公告)号：US20160343861A1

公开(公告)日：2016-11-24

申请号：US14719829

申请日：2015-05-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie ,  Derrick Liu ,  Soon-Cheon Seo ,  Stuart A. Sieg

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

Abstract translation: 提供一种半导体结构，其包括具有端壁并从衬底向上延伸的半导体鳍部。 栅极结构跨越半导体鳍片部分的一部分。 第一组栅极间隔物位于栅极结构的相对的侧壁表面上; 并且第二组栅极间隔物位于第一组栅极间隔物的侧壁上。 第二组栅极间隔物的一个栅极间隔物具有直接接触半导体鳍片部分的端壁的下部。

公开(公告)号：US09502411B1

公开(公告)日：2016-11-22

申请号：US14833363

申请日：2015-08-24

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie ,  Stuart A. Sieg

IPC: H01L27/088 ,  H01L27/12 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/845 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/76213 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.

Abstract translation: 一种用于在衬底上形成翅片的方法包括图案化和蚀刻第一半导体材料的层以限定应变翅片，在鳍片上沉积第二半导体材料层，第二半导体材料可操作以将应变保持在 应变翅片，蚀刻以去除第二半导体材料的一部分以限定暴露鳍片的一部分的腔，蚀刻以去除鳍的暴露部分，使得鳍分成第一段和第二段，以及 在空腔中沉积绝缘体材料，绝缘体材料接触翅片的第一段和翅片的第二段。

公开(公告)号：US09293375B2

公开(公告)日：2016-03-22

申请号：US14260724

申请日：2014-04-24

Applicant: International Business Machines Corporation

Inventor： Kevin S. Petrarca ,  Stuart A. Sieg ,  Theodorus E. Standaert

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/762 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/308 ,  H01L21/311 ,  H01L21/02 ,  H01L29/78 ,  H01L21/033 ,  H01L27/092

CPC classification number: H01L21/823431 ,  H01L21/02123 ,  H01L21/0337 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A trench isolation structure is formed beneath a topmost surface of a semiconductor substrate. A mandrel structure having a bottommost surface that straddles a sidewall edge of the underlying trench isolation structure is then formed. Nitride spacers are formed on sidewalls of the mandrel structure and thereafter the mandrel structure is removed. A dielectric oxide material is then formed having a topmost surface that is coplanar with a topmost surface of each remaining nitride spacer. Each nitride spacer is removed and thereafter a semiconductor fin is epitaxially grown within a cavity in the dielectric oxide material which exposes a topmost surface of the semiconductor substrate.

Abstract translation: 沟槽隔离结构形成在半导体衬底的最上表面之下。 然后形成具有跨越下面的沟槽隔离结构的侧壁边缘的最底表面的心轴结构。 氮化物间隔件形成在心轴结构的侧壁上，然后去除心轴结构。 然后形成电介质氧化物材料，其具有与每个剩余的氮化物间隔物的最上表面共面的最顶表面。 去除每个氮化物间隔物，然后在暴露半导体衬底的最上表面的电介质氧化物材料的腔内外延生长半导体鳍。

公开(公告)号：US20140256130A1

公开(公告)日：2014-09-11

申请号：US13785816

申请日：2013-03-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Kevin S. Petrarca ,  Stuart A. Sieg

IPC: H01L21/768

CPC classification number: H01L23/544 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/54426 ,  H01L2223/54433 ,  H01L2223/54453 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for printing a wafer ID on a wafer, the method comprises identifying a wafer ID on a back side of the wafer. Subsequently, etching a plurality of recesses, consistent in size with chip features of the wafer, into the front side of the wafer, such that the plurality of recesses depicts the wafer ID. The method further comprises filling the recesses with a metal.

Abstract translation: 一种用于在晶片上印刷晶片ID的方法，所述方法包括在晶片的背面识别晶片ID。 随后，将与晶片的芯片特征尺寸一致的多个凹槽蚀刻到晶片的前侧，使得多个凹槽示出晶片ID。 该方法还包括用金属填充凹部。

公开(公告)号：US10811508B2

公开(公告)日：2020-10-20

申请号：US15803918

申请日：2017-11-06

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Fee Li Lie ,  Stuart A. Sieg ,  Junli Wang

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786 ,  H01L29/78 ,  H01L27/02 ,  H01L21/8234

Abstract: Embodiments of the invention are directed to methods of forming a configuration of semiconductor devices. A non-limiting example method includes forming a first channel fin structure over a performance region of a major surface of a substrate. A first gate structure is formed along at least a portion of a sidewall surface of the first channel fin structure, where the first gate structure includes a first gate thickness dimension. A second channel fin structure is formed over a density region of the major surface of the substrate. A second gate structure is formed along at least a portion of a sidewall surface of the second channel fin structure, where the second gate structure includes a second gate thickness dimension that is less than the first gate thickness dimension.

公开(公告)号：US20200294803A1

公开(公告)日：2020-09-17

申请号：US16353641

申请日：2019-03-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Wenyu Xu ,  Stuart A. Sieg ,  Ruilong Xie ,  John R. Sporre

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/78

Abstract: A method of forming adjacent fin field effect transistor devices is provided. The method includes forming at least two vertical fins in a column on a substrate, depositing a gate dielectric layer on the vertical fins, and depositing a work function material layer on the gate dielectric layer. The method further includes depositing a protective liner on the work function material layer, and forming a fill layer on the protective liner. The method further includes removing a portion of the fill layer to form an opening between an adjacent pair of two vertical fins, where the opening exposes a portion of the protective liner. The method further includes depositing an etch-stop layer on the exposed surfaces of the fill layer and protective liner, forming a gauge layer in the opening to a predetermined height, and removing the exposed portion of the etch-stop layer to form an etch-stop segment.

公开(公告)号：US20190287957A1

公开(公告)日：2019-09-19

申请号：US15923683

申请日：2018-03-16

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Stuart A. Sieg ,  Junli Wang

IPC: H01L27/02 ,  H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238

Abstract: A semiconductor structure includes a vertical transport static random-access memory (SRAM) cell having a first active region and a second active region. The first active region and the second active region are linearly arranged in first and second rows, respectively. The first row of the first active region includes a first pull-up transistor, a first pull-down transistor and a first pass gate transistor, and the second row of the second active region includes a second pull-up transistor, a second pull-down transistor and a second pass gate transistor. A first gate region of the first active region extends orthogonal from the first row to the second active region, and a second gate region of the second active region extends orthogonal from the second row to the first active region.

公开(公告)号：US10361129B1

公开(公告)日：2019-07-23

申请号：US15983907

申请日：2018-05-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Stuart A. Sieg ,  Yann Mignot ,  Christopher J. Waskiewicz ,  Hemanth Jagannathan ,  Eric Miller ,  Indira Seshadri

IPC: H01L21/30 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/3065 ,  H01L27/088

Abstract: Methods and devices for forming multiple fin lengths includes forming a material stack on vertical fins. A plurality of mandrels are formed on the material stack. Spacers are formed along the plurality of mandrels with the spacers width being a length of short fins. One or more of the plurality of mandrels are removed. The material stack is patterned to form the short fins beneath the spacers and long fins. The vertical fins are cut with the pattern of the material stack to form the short fins and the long fins.