公开(公告)号：US10032674B2

公开(公告)日：2018-07-24

申请号：US14960968

申请日：2015-12-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Joshua M. Rubin ,  Balasubramanian Pranatharthiharan

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/535 ,  H01L29/49 ,  H01L29/161 ,  H01L27/088 ,  H01L29/417

Abstract: A method for forming contacts on a semiconductor device includes forming trenches by etching an etch stop layer formed on an interlayer dielectric and etching the interlayer dielectric to expose source and drain regions between gate structures and depositing conductive material in the trenches and over the etch stop layer to a height above the etch stop layer. A resist is patterned on the conductive material with shapes over selected source and drain regions. The conductive material is subtractively etched to remove the conductive material from over the etch stop layer and to recess the conductive material into the trenches without the shapes to form self-aligned contacts below the shapes and lines in the trenches.

公开(公告)号：US20180083134A1

公开(公告)日：2018-03-22

申请号：US15819306

申请日：2017-11-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Terence B. Hook ,  Joshua M. Rubin ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L21/84 ,  H01L29/08 ,  H01L27/12 ,  H01L29/06

CPC classification number: H01L29/0649 ,  H01L21/02642 ,  H01L21/76254 ,  H01L21/76256 ,  H01L21/76283 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1604 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method for forming a semiconductor device comprises forming a fin in a bulk semiconductor substrate and depositing a first insulator layer over portions of the bulk semiconductor substrate adjacent to the fin. The method further includes removing portions of the first insulator layer to reduce a thickness of the first insulator layer and expose a sidewall of the fin. An etch stop layer is deposited on the first insulator layer. A gate stack is formed over a channel region of the fin and over portions of the etch stop layer. A portion of the bulk semiconductor substrate is removed to expose portions of the etch stop layer and the fin, and a second insulator layer is deposited over exposed portions of the fin and the etch stop layer.

公开(公告)号：US20180047847A1

公开(公告)日：2018-02-15

申请号：US15791691

申请日：2017-10-24

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Pouya Hashemi ,  Alexander Reznicek ,  Joshua M. Rubin ,  Robin M. Schulz

IPC: H01L29/78 ,  H01L21/324 ,  H01L29/66 ,  H01L29/165 ,  H01L29/417 ,  H01L21/02 ,  H01L21/8234

CPC classification number: H01L29/7848 ,  H01L21/02318 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/324 ,  H01L21/823418 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7853

Abstract: A thermal mixing process is employed to convert a portion of a silicon germanium alloy fin having a first germanium content and an overlying non-doped epitaxial silicon source material into a silicon germanium alloy source structure having a second germanium content that is less than the first germanium content, to convert another portion of the silicon germanium alloy fin and an overlying non-doped epitaxial silicon drain material into a silicon germanium alloy drain structure having the second germanium content, and to provide a tensile strained silicon germanium alloy fin portion having the first germanium content. A dopant is then introduced into the silicon germanium alloy source structure and into the silicon germanium alloy drain structure.

公开(公告)号：US20170317052A1

公开(公告)日：2017-11-02

申请号：US15651990

申请日：2017-07-17

Applicant: International Business Machines Corporation

Inventor： Joshua M. Rubin

IPC: H01L23/00 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L24/83 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53228 ,  H01L25/00 ,  H01L2224/8303 ,  H01L2224/83896

Abstract: Wafer bonding edge protection techniques are provided. In one aspect, a method of forming Cu interconnects in a wafer includes: forming a dielectric layer on the wafer; forming a first mask on the dielectric layer; patterning the first mask with a footprint/location of the Cu interconnects, wherein the patterning of the first mask is performed over an entire surface of the wafer; forming a second mask on the first mask, wherein the second mask covers a portion of the patterned first mask at an edge region of the wafer; patterning trenches in the dielectric layer through the first mask and the second mask, wherein the second mask blocks formation of the trenches at the edge region of the wafer and thereby provides edge protection during patterning of the trenches; and forming the Cu interconnects in the trenches. A wafer bonding method and interconnect structure are also provided.

公开(公告)号：US20170294534A1

公开(公告)日：2017-10-12

申请号：US15364573

申请日：2016-11-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Terence B. Hook ,  Joshua M. Rubin ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L21/84 ,  H01L29/08 ,  H01L27/12 ,  H01L29/06

CPC classification number: H01L29/0649 ,  H01L21/02642 ,  H01L21/76254 ,  H01L21/76256 ,  H01L21/76283 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1604 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method for forming a semiconductor device comprises forming a fin in a bulk semiconductor substrate and depositing a first insulator layer over portions of the bulk semiconductor substrate adjacent to the fin. The method further includes removing portions of the first insulator layer to reduce a thickness of the first insulator layer and expose a sidewall of the fin. An etch stop layer is deposited on the first insulator layer. A gate stack is formed over a channel region of the fin and over portions of the etch stop layer. A portion of the bulk semiconductor substrate is removed to expose portions of the etch stop layer and the fin, and a second insulator layer is deposited over exposed portions of the fin and the etch stop layer.

公开(公告)号：US09735062B1

公开(公告)日：2017-08-15

申请号：US15172472

申请日：2016-06-03

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Nicolas J. Loubet ,  Alexander Reznicek ,  Joshua M. Rubin

IPC: H01L21/84 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/161 ,  H01L21/02 ,  H01L27/12 ,  H01L21/3065

CPC classification number: H01L21/823807 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02642 ,  H01L21/02658 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/161

Abstract: After forming a blanket silicon germanium (SiGe) layer over a thinned silicon (Si) layer of a silicon-on-insulator (SOI) substrate, a portion of the SiGe layer located in an n-type FET (nFET) region of the SOI substrate is recessed, while masking another portion of the SiGe layer located in a p-type FET (pFET) region of the SOI substrate. The recessed portion of the SiGe layer in the nFET region is subsequently removed with an in-situ pre-clean etch. An epitaxial Si layer is re-grown in the nFET region over a portion of the thinned Si layer that is exposed by the removal of the recessed portion of the SiGe layer.

公开(公告)号：US20250022800A1

公开(公告)日：2025-01-16

申请号：US18222193

申请日：2023-07-14

Applicant: International Business Machines Corporation

Inventor： Timothy J. Chainer ,  Joshua M. Rubin ,  John W. Golz ,  Mounir Meghelli ,  Todd Edward Takken ,  Arvind Kumar

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L25/10

Abstract: A 3D chip (or wafer) stack is provided in which a customized redistribution layer is located between each semiconductor wafer of the chip (or wafer) stack. The customized redistribution layer connects functional die sites on a first semiconductor wafer to functional die sites on a second semiconductor wafer, while by-passing non-functional die sites on the second semiconductor wafer.

公开(公告)号：US12167612B2

公开(公告)日：2024-12-10

申请号：US17352626

申请日：2021-06-21

Applicant: International Business Machines Corporation

Inventor： Arvind Kumar ,  Joshua M. Rubin

IPC: H10B61/00 ,  G11C11/56 ,  H10N50/80 ,  H10N50/01

Abstract: A memory device includes a semiconductor device on a wafer. The semiconductor device includes a gate structure, a first source/drain region, and a second source/drain region. The gate structure is on the first side of the wafer. The first source/drain region is also on the first side of the wafer, and contacts a first end of the gate structure. The second source/drain region is on the second side of the wafer and extends into the first side to contact a second end of the gate structure. The memory device further includes a memory storage element on the second side of the wafer. The memory storage element contacts the second source/drain region.

公开(公告)号：US20240332130A1

公开(公告)日：2024-10-03

申请号：US18192989

申请日：2023-03-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Joshua M. Rubin ,  Marc A. Bergendahl

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L21/6835 ,  H01L2221/68359

Abstract: Aspects of the present invention provide a semiconductor structure. The semiconductor structure may include a first horizontally-fabricated semiconductor die section and a vertical interconnect (VI) die perpendicularly oriented to the first semiconductor die section. The VI die may include vertical metal interconnect lines electrically connecting components above and below the VI die.

公开(公告)号：US20240203822A1

公开(公告)日：2024-06-20

申请号：US18083554

申请日：2022-12-18

Applicant: International Business Machines Corporation

Inventor： Evan Colgan ,  Jae-Woong Nah ,  Katsuyuki Sakuma ,  Kamal K. Sikka ,  Joshua M. Rubin ,  Frank Robert Libsch

IPC: H01L23/473 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/473 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L25/0655 ,  H01L25/18 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2924/0665

Abstract: A chip and cooler assembly includes an active or passive interposer that has a front side and a back side. Integrated circuit chips are mounted onto the back side of the interposer. Each of the chips has a front side that is attached to the interposer and a back side that faces away from the interposer. Gaps separate the chips. The assembly also includes a frame that is fitted into the gaps between the chips. The frame is CTE-matched to the chips. The frame and the chips define a back side surface. A cooler module is attached to the back side surface. The cooler module is CTE-matched to the chips. The cooler module includes a microchannel cooler that is disposed directly against the back sides of the chips and a manifold that is attached to the microchannel cooler opposite the chips. The manifold is CTE-matched to the microchannel cooler.