公开(公告)号：US08349733B2

公开(公告)日：2013-01-08

申请号：US12132187

申请日：2008-06-03

申请人： Takaharu Yamano

发明人： Takaharu Yamano

IPC分类号： H01L21/768

CPC分类号： H01L21/76898 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49833 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K1/0306 ,  H05K3/205 ,  H05K3/4038 ,  H05K3/423 ,  H05K3/4605 ,  H05K3/4647 ,  H05K2201/0979 ,  H05K2203/0376 ,  H05K2203/063 ,  H05K2203/0733 ,  H01L2924/00

摘要： A manufacturing method of a substrate with through electrodes, comprising a substrate having through holes, and through electrodes received in the through holes, includes a through electrode formation step of forming the through electrodes on a support plate, a substrate formation step of forming the substrate, a through electrode reception step of stacking the substrate on the support plate 45 and receiving the through electrodes in the through holes, a resin filling step of filling gaps between side surfaces of the through electrodes and inner walls of the through holes of the substrate 11 with a resin, and a support plate removal step of removing the support plate after the resin filling step.

摘要翻译： 具有贯通电极的基板的制造方法，具有通孔的基板和贯通孔内的电极，具有在支撑板上形成贯通电极的贯通电极形成工序，形成基板的基板形成工序 通孔电极接收步骤，将基板堆叠在支撑板45上并接收通孔中的通孔;树脂填充步骤，填充通孔的侧表面之间的间隙和基板11的通孔的内壁 以及在树脂填充步骤之后移除支撑板的支撑板移除步骤。

公开(公告)号：US08211754B2

公开(公告)日：2012-07-03

申请号：US12581486

申请日：2009-10-19

申请人： Takaharu Yamano

发明人： Takaharu Yamano

IPC分类号： H01L21/58

CPC分类号： H01L23/3128 ,  H01L21/561 ,  H01L21/563 ,  H01L23/49816 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/838 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor device including a semiconductor chip encapsulated by an encapsulation resin and a manufacturing method thereof, in which a size reduction may be attempted. The device includes a semiconductor chip, an external connection terminal pad electrically connected to the semiconductor chip, and an encapsulation resin encapsulating the semiconductor chip, wherein a wiring pattern on which the external connection terminal pad is formed is provided between the semiconductor chip and the external connection terminal pad, and the semiconductor chip is flip-chip bonded to the wiring pattern.

摘要翻译： 包括由封装树脂封装的半导体芯片的半导体器件及其制造方法，其中可以尝试减小尺寸。 该器件包括半导体芯片，与半导体芯片电连接的外部连接端子焊盘以及封装半导体芯片的封装树脂，其中，形成有外部连接端子焊盘的布线图案设置在半导体芯片与外部 连接端子焊盘，并且半导体芯片被倒装芯片接合到布线图案。

公开(公告)号：US20120153507A1

公开(公告)日：2012-06-21

申请号：US13331121

申请日：2011-12-20

申请人： Syota MIKI ,  Takaharu Yamano ,  Toshio Kobayashi

发明人： Syota MIKI ,  Takaharu Yamano ,  Toshio Kobayashi

IPC分类号： H01L23/48 ,  H01L21/56

CPC分类号： H01L21/568 ,  H01L23/3128 ,  H01L24/19 ,  H01L2224/12105 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00

摘要： A method include disposing a semiconductor chip having an electrode pad formed on a circuit forming surface on one surface of a support so that the electrode pad contacts with the one surface of the support, forming a first insulating layer on the one surface of the support so that the first insulating layer covers at least a side surface of the semiconductor chip, removing the support and forming an interconnection terminal on the electrode pad, forming a second insulating layer on the circuit forming surface of the semiconductor chip and the first insulating layer so that the second insulating layer covers the interconnection terminal, exposing an end portion of the interconnection terminal from a top surface of the second insulating layer, and forming a wiring pattern that is electrically connected to the end portion of the interconnection terminal, on the top surface of the second insulating layer.

摘要翻译： 一种方法包括在支撑体的一个表面上设置具有形成在电路形成表面上的电极焊盘的半导体芯片，使得电极焊盘与支撑体的一个表面接触，在支撑体的一个表面上形成第一绝缘层， 第一绝缘层至少覆盖半导体芯片的侧表面，去除支撑并在电极焊盘上形成互连端子，在半导体芯片的电路形成表面和第一绝缘层上形成第二绝缘层，使得 所述第二绝缘层覆盖所述互连端子，将所述互连端子的端部从所述第二绝缘层的顶表面露出，并且形成与所述互连端子的端部电连接的布线图案， 第二绝缘层。

公开(公告)号：US20110256662A1

公开(公告)日：2011-10-20

申请号：US13167203

申请日：2011-06-23

申请人： Takaharu YAMANO ,  Hajime IIZUKA ,  Hideaki SAKAGUCHI ,  Toshio KOBAYASHI ,  Tadashi ARAI ,  Tsuyoshi KOBAYASHI ,  Tetsuya KOYAMA ,  Kiyoaki IIDA ,  Tomoaki MASHIMA ,  Koichi TANAKA ,  Yuji KUNIMOTO ,  Takashi YANAGISAWA

发明人： Takaharu YAMANO ,  Hajime IIZUKA ,  Hideaki SAKAGUCHI ,  Toshio KOBAYASHI ,  Tadashi ARAI ,  Tsuyoshi KOBAYASHI ,  Tetsuya KOYAMA ,  Kiyoaki IIDA ,  Tomoaki MASHIMA ,  Koichi TANAKA ,  Yuji KUNIMOTO ,  Takashi YANAGISAWA

IPC分类号： H01L21/56

CPC分类号： H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/162 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/207 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/185 ,  H05K1/186 ,  H05K3/20 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4644 ,  H05K2201/10007 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  H01L2924/00

摘要： A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip.

摘要翻译： 公开了一种制造芯片嵌入式基板的方法。 该方法包括将半导体芯片安装在其上形成有第一布线的第一基板上的第一步骤; 以及将第一基板与形成有第二布线的第二基板接合的第二步骤。 在第二步骤中，将半导体芯片封装在第一基板和第二基板之间，并且在第一布线和第二布线之间形成电连接，以形成连接到半导体芯片的多层布线。

公开(公告)号：US07955454B2

公开(公告)日：2011-06-07

申请号：US11516737

申请日：2006-09-07

申请人： Takaharu Yamano ,  Kosaku Harayama ,  Hiroyuki Kato ,  Tetsuya Koyama

发明人： Takaharu Yamano ,  Kosaku Harayama ,  Hiroyuki Kato ,  Tetsuya Koyama

IPC分类号： B29C65/00 ,  A41G1/00 ,  B32B37/00 ,  C23F3/00

CPC分类号： H05K3/4661 ,  H05K3/0035 ,  H05K3/108 ,  H05K3/381 ,  H05K2203/0554 ,  H05K2203/1152 ,  Y10T156/10 ,  Y10T156/1057 ,  Y10T156/1082

摘要： The method for forming wiring includes: laminating a thermosetting resin film and a metallic foil on an insulating substrate where base-layer wiring is formed, a mat surface of the metallic foil facing the resin film, pressing the film and the foil with application of heat; forming an opening in the metallic foil to expose a part of the insulating resin layer in which a via hole is to be formed; forming the via hole in the insulating resin layer by using as a mask the metallic foil; performing a desmear process of the via hole via the opening of the metallic foil; removing the metallic foil; forming an electroless-plated layer that covers the top surface of the insulating resin layer, a side surface of the via hole and a top surface of the base-layer wiring; and forming wiring including an electroplated layer on the electroless-plated layer.

摘要翻译： 形成布线的方法包括：在形成基底布线的绝缘基板上层叠热固性树脂膜和金属箔，金属箔的面向树脂膜的垫表面，施加热量来压制膜和箔 ; 在所述金属箔中形成开口以暴露要形成通孔的绝缘树脂层的一部分; 通过使用金属箔作为掩模在绝缘树脂层中形成通孔; 经由金属箔的开口进行通孔的去污处理; 去除金属箔; 形成覆盖绝缘树脂层的顶面，通孔的侧面和基底布线的顶面的无电镀层; 以及在所述化学镀层上形成包括电镀层的布线。

公开(公告)号：US07884484B2

公开(公告)日：2011-02-08

申请号：US11372916

申请日：2006-03-10

申请人： Takaharu Yamano ,  Masahiro Sunohara ,  Hajime Iizuka ,  Tetsuya Koyama

发明人： Takaharu Yamano ,  Masahiro Sunohara ,  Hajime Iizuka ,  Tetsuya Koyama

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/5383 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/18 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/81 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/136 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H01L2924/381 ,  H05K1/185 ,  H05K3/4644 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/0401

摘要： A wiring board includes an insulating layer in which a semiconductor chip is embedded, and a wiring structure connected to the semiconductor chip. A reinforcing member reinforcing the insulating layer is embedded in the insulating layer. This enables reduction in a thickness of the wiring board and a suppression of warpage of the wiring board.

摘要翻译： 布线基板包括嵌入有半导体芯片的绝缘层和与半导体芯片连接的布线结构。 加强绝缘层的加强构件嵌入在绝缘层中。 这样可以减少布线板的厚度和抑制布线板的翘曲。

公开(公告)号：US07884453B2

公开(公告)日：2011-02-08

申请号：US11856354

申请日：2007-09-17

申请人： Takaharu Yamano

发明人： Takaharu Yamano

IPC分类号： H01L23/34

CPC分类号： H01L23/3128 ,  H01L21/561 ,  H01L21/563 ,  H01L23/49816 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/838 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/0555 ,  H01L2224/0556

摘要： The present invention relates to a semiconductor device including a semiconductor chip encapsulated by an encapsulation resin and a manufacturing method thereof, and an object of the invention is to provide the semiconductor chip and its manufacturing method in which the reduction in size may be attempted. It includes a semiconductor chip 15, an external connection terminal pad 18 electrically connected to the semiconductor chip 15, and an encapsulation resin 16 encapsulating the semiconductor chip 15, wherein a wiring pattern 12 on which the external connection terminal pad 18 is formed is provided between the semiconductor chip 15 and the external connection terminal pad 18, and the semiconductor chip 15 is flip-chip bonded to the wiring pattern 12.

摘要翻译： 本发明涉及包含由封装树脂封装的半导体芯片的半导体器件及其制造方法，本发明的目的是提供可以尝试减小尺寸的半导体芯片及其制造方法。 它包括半导体芯片15，电连接到半导体芯片15的外部连接端子焊盘18和封装半导体芯片15的封装树脂16，其中形成有外部连接端子焊盘18的布线图案12设置在 半导体芯片15和外部连接端子焊盘18以及半导体芯片15被倒装芯片接合到布线图案12。

公开(公告)号：US20100022035A1

公开(公告)日：2010-01-28

申请号：US12588076

申请日：2009-10-02

申请人： Takaharu Yamano

发明人： Takaharu Yamano

IPC分类号： H01L21/50

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L23/585 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/02333 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/06135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/85399 ,  H01L2225/06562 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： There are provided a plurality of semiconductor apparatuses judged as good items in electrical and functional inspections while having internal connection terminals disposed on electrode pads of semiconductor chips, resin layers which are disposed on surfaces of the semiconductor chips in which the electrode pads are formed and expose the internal connection terminals, and wiring patterns which are disposed on the resin layers and are connected to the internal connection terminals, a wiring substrate on which the plurality of semiconductor apparatuses are stepwise stacked, the wiring substrate electrically connected to the plurality of semiconductor apparatuses, and a sealing resin with which the plurality of semiconductor apparatuses are sealed.

摘要翻译： 在半导体芯片的电极焊盘上设置有内部连接端子，设置在形成有电极焊盘的半导体芯片的表面上的树脂层，露出的电气和功能检查中判断为好的项目的多个半导体装置 内部连接端子和配置在树脂层上并与内部连接端子连接的布线图案，多个半导体装置分层堆叠的布线基板，与多个半导体装置电连接的布线基板， 以及密封多个半导体装置的密封树脂。

公开(公告)号：US20090302471A1

公开(公告)日：2009-12-10

申请号：US12476454

申请日：2009-06-02

申请人： Takaharu YAMANO

发明人： Takaharu YAMANO

IPC分类号： H01L23/535 ,  H01L21/768

CPC分类号： H01L24/11 ,  H01L23/556 ,  H01L2224/02333 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01092 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00014

摘要： There is provided a semiconductor device including a semiconductor substrate on which a plurality of semiconductor chips having electrode pads is formed, an internal connection terminal provided on each of the electrode pads, an insulating layer provided to cover the plurality of semiconductor chips and the internal connection terminals, and a wiring pattern connected to the internal connection terminals across the insulating layer. This semiconductor device is characterized in that the insulating layer is configured to contain an alpha ray blocking material including polyimide and/or a polyimide-based compound.

摘要翻译： 提供了一种半导体器件，包括其上形成有多个具有电极焊盘的半导体芯片的半导体衬底，设置在每个电极焊盘上的内部连接端子，设置成覆盖多个半导体芯片的绝缘层和内部连接 端子，以及连接到穿过绝缘层的内部连接端子的布线图案。 该半导体器件的特征在于，绝缘层被配置为包含包含聚酰亚胺和/或聚酰亚胺基化合物的α射线阻挡材料。

公开(公告)号：US20080299768A1

公开(公告)日：2008-12-04

申请号：US12132187

申请日：2008-06-03

申请人： Takaharu Yamano

发明人： Takaharu Yamano

IPC分类号： H01L21/768

CPC分类号： H01L21/76898 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49833 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K1/0306 ,  H05K3/205 ,  H05K3/4038 ,  H05K3/423 ,  H05K3/4605 ,  H05K3/4647 ,  H05K2201/0979 ,  H05K2203/0376 ,  H05K2203/063 ,  H05K2203/0733 ,  H01L2924/00

摘要： A manufacturing method of a substrate with through electrodes, comprising a substrate having through holes, and through electrodes received in the through holes, includes a through electrode formation step of forming the through electrodes on a support plate, a substrate formation step of forming the substrate, a through electrode reception step of stacking the substrate on the support plate 45 and receiving the through electrodes in the through holes, a resin filling step of filling gaps between side surfaces of the through electrodes and inner walls of the through holes of the substrate 11 with a resin, and a support plate removal step of removing the support plate after the resin filling step.

摘要翻译： 具有贯通电极的基板的制造方法，具有通孔的基板和贯通孔内的电极，具有在支撑板上形成贯通电极的贯通电极形成工序，形成基板的基板形成工序 通孔电极接收步骤，将基板堆叠在支撑板45上并在通孔中容纳通孔;树脂填充步骤，填充通孔的侧表面之间的间隙和基板11的通孔的内壁 以及在树脂填充步骤之后移除支撑板的支撑板移除步骤。