公开(公告)号：US11581217B2

公开(公告)日：2023-02-14

申请号：US17346756

申请日：2021-06-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tzu-Yang Lin ,  Cheng-Han Wu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/033 ,  H01L21/027

Abstract: A method for forming openings in an underlayer includes: forming a photoresist layer on an underlayer formed on a substrate; exposing the photoresist layer; forming photoresist patterns by developing the exposed photoresist layer, the photoresist patterns covering regions of the underlayer in which the openings are to be formed; forming a liquid layer over the photoresist patterns; after forming the liquid layer, performing a baking process so as to convert the liquid layer to an organic layer in a solid form; performing an etching back process to remove a portion of the organic layer on a level above the photoresist patterns; removing the photoresist patterns, so as to expose portions of the underlayer by the remaining portion of the organic layer; forming the openings in the underlayer by using the remaining portion of the organic layer as an etching mask; and removing the remaining portion of the organic layer.

公开(公告)号：US20190123204A1

公开(公告)日：2019-04-25

申请号：US16229118

申请日：2018-12-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chin-Hsiang Lin ,  Tai-Chun Huang ,  Tien-I Bao

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/528 ,  H01L29/66 ,  H01L21/033 ,  H01L21/02

Abstract: An embodiment is a method including recessing a gate electrode over a semiconductor fin on a substrate to form a first recess from a top surface of a dielectric layer, forming a first mask in the first recess over the recessed gate electrode, recessing a first conductive contact over a source/drain region of the semiconductor fin to form a second recess from the top surface of the dielectric layer, and forming a second mask in the second recess over the recessed first conductive contact.

公开(公告)号：US09985134B1

公开(公告)日：2018-05-29

申请号：US15455603

申请日：2017-03-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chin-Hsiang Lin ,  Tai-Chun Huang ,  Tien-I Bao

IPC: H01L21/82 ,  H01L29/78 ,  H01L23/528 ,  H01L29/66 ,  H01L21/033 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8234

CPC classification number: H01L29/7851 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/76843 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5283 ,  H01L29/66545 ,  H01L29/66795

Abstract: An embodiment is a method including recessing a gate electrode over a semiconductor fin on a substrate to form a first recess from a top surface of a dielectric layer, forming a first mask in the first recess over the recessed gate electrode, recessing a first conductive contact over a source/drain region of the semiconductor fin to form a second recess from the top surface of the dielectric layer, and forming a second mask in the second recess over the recessed first conductive contact.

公开(公告)号：US09927707B2

公开(公告)日：2018-03-27

申请号：US15470332

申请日：2017-03-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Yu Liu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/32 ,  G03F7/039 ,  H01L21/027 ,  G03F7/09 ,  G03F7/20 ,  G03F7/38 ,  C08F220/18 ,  C08F220/26 ,  C11D11/00

CPC classification number: G03F7/322 ,  C08F220/18 ,  C08F220/26 ,  C11D11/0047 ,  G03F7/039 ,  G03F7/091 ,  G03F7/2004 ,  G03F7/327 ,  G03F7/38 ,  H01L21/0274 ,  H01L21/0275 ,  H01L21/0276

Abstract: A method for lithography patterning includes forming a material layer over a substrate; exposing a portion of the material layer to a radiation; and removing the exposed portion of the material layer in a developer, resulting in a patterned material layer. The developer comprises water, an organic solvent, and a basic solute. In an embodiment, the basic solute is less than 30% of the developer by weight.

公开(公告)号：US09764364B2

公开(公告)日：2017-09-19

申请号：US14581509

申请日：2014-12-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ying-Hsueh Chang Chien ,  Chin-Hsiang Lin ,  Chi-Ming Yang ,  Ming-Hsi Yeh ,  Shao-Yen Ku

IPC: H01L21/30 ,  B08B3/12 ,  H01L21/67 ,  B08B3/02

CPC classification number: B08B3/12 ,  B08B3/02 ,  H01L21/67028 ,  H01L21/6704

Abstract: A movable wafer probe may include: an immersion hood including a top body portion and a bottom foot portion, the top body portion having first inner sidewalls surrounding a top opening, the bottom foot portion having second inner sidewalls surrounding a bottom opening; a transducer disposed above the bottom opening and within the top opening, the transducer spaced apart from the first inner sidewalls of the top body portion by a first spacing, the first spacing forming a fluid exhaust port; and a fluid input port extending through the transducer, a bottom end of the fluid input port opening to the bottom opening.

公开(公告)号：US09735276B2

公开(公告)日：2017-08-15

申请号：US13918684

申请日：2013-06-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hang Tung ,  Chin-Hsiang Lin ,  Cheng-Hung Chang ,  Sey-Ping Sun

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7856 ,  H01L29/41791 ,  H01L29/66803 ,  H01L29/7839 ,  H01L29/785 ,  H01L2029/7858

Abstract: Non-planar transistors and methods of fabrication thereof are described. In an embodiment, a method of forming a non-planar transistor includes forming a channel region on a first portion of a semiconductor fin, the semiconductor fin having a top surface and sidewalls. A gate electrode is formed over the channel region of the semiconductor fin, and an in-situ doped semiconductor layer is grown on the top surface and the sidewalls of the semiconductor fin on opposing sides of the gate electrode using a selective epitaxial growth process. At least a part of the doped semiconductor layer is converted to form a dopant rich region.

公开(公告)号：US09640487B2

公开(公告)日：2017-05-02

申请号：US14688766

申请日：2015-04-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Hsiang Tseng ,  Chao-Hsiung Wang ,  Chin-Hsiang Lin ,  Heng-Hsin Liu ,  Ho-Ping Chen ,  Jui-Chun Peng

IPC: G01B11/00 ,  H01L23/544 ,  H01L21/66 ,  G03F9/00

CPC classification number: H01L23/544 ,  G03F9/7011 ,  G03F9/7084 ,  H01L22/10 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wafer alignment apparatus includes a light source, a light detection device, and a rotation device configured to rotate a first wafer and a second wafer. The light source is configured to provide a first light directed to the first wafer and a second light directed to the second wafer. The light detection device is configured to detect reflected light intensity from the first wafer to find a position of at least one wafer alignment mark of the first wafer and to detect reflected light intensity from the second wafer to find a position of at least one wafer alignment mark of the second wafer.

公开(公告)号：US09449889B2

公开(公告)日：2016-09-20

申请号：US14684953

申请日：2015-04-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Lin Chang ,  Chih-Hong Hwang ,  Nai-Han Cheng ,  Chi-Ming Yang ,  Chin-Hsiang Lin

IPC: H01L21/66 ,  H01J37/244 ,  H01J37/317 ,  H01L21/265

CPC classification number: H01L22/10 ,  H01J37/244 ,  H01J37/3171 ,  H01J2237/24542 ,  H01J2237/30455 ,  H01J2237/31703 ,  H01L21/265

Abstract: A method comprises placing a wafer and a ring-shaped beam profiler on a wafer holder, wherein the ring-shaped beam profiler is adjacent to the wafer, moving a first sensor and a second sensor simultaneously with the wafer holder, receiving a first sensed signal and a second sensed signal from the first sensor and the second sensor respectively and adjusting an ion beam generated by an ion beam generator based upon the first sensed signal and the second sensed signal.

Abstract translation: 一种方法包括将晶片和环形光束轮廓仪放置在晶片保持器上，其中环形光束轮廓仪邻近晶片，与晶片保持器同时移动第一传感器和第二传感器，接收第一感测信号 以及分别来自第一传感器和第二传感器的第二检测信号，并且基于第一感测信号和第二感测信号调整由离子束发生器产生的离子束。

公开(公告)号：US09368452B2

公开(公告)日：2016-06-14

申请号：US14182912

申请日：2014-02-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Soon-Kang Huang ,  Han-Hsin Kuo ,  Chi-Ming Yang ,  Shwang-Ming Jeng ,  Chin-Hsiang Lin

IPC: H01L23/48 ,  H01L23/538 ,  H01L21/02 ,  H01L21/28 ,  H01L21/768 ,  H01L29/78 ,  H01L21/67 ,  H01L29/49

CPC classification number: H01L23/5386 ,  H01L21/02074 ,  H01L21/28079 ,  H01L21/67011 ,  H01L21/7684 ,  H01L29/495 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides a method of fabricating a semiconductor device, a semiconductor device fabricated by such a method, and a chemical mechanical polishing (CMP) tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device includes providing an integrated circuit (IC) wafer including a metal conductor in a trench of a dielectric layer over a substrate, and performing a chemical mechanical polishing (CMP) process to planarize the metal conductor and the dielectric layer. The method further includes cleaning the planarized metal conductor and dielectric layer to remove residue from the CMP process, rinsing the cleaned metal conductor and dielectric layer with an alcohol, and drying the rinsed metal conductor and dielectric layer in an inert gas environment.

Abstract translation: 本公开提供了一种制造半导体器件的方法，通过这种方法制造的半导体器件和用于执行这种方法的化学机械抛光（CMP）工具。 在一个实施例中，制造半导体器件的方法包括在衬底上的电介质层的沟槽中提供包括金属导体的集成电路（IC）晶片，以及执行化学机械抛光（CMP）工艺以平坦化金属导体 和电介质层。 该方法还包括清洁平坦化的金属导体和电介质层以除去CMP工艺中的残留物，用醇漂洗清洁的金属导体和介电层，并在惰性气体环境中干燥漂洗的金属导体和电介质层。

公开(公告)号：US20150140763A1

公开(公告)日：2015-05-21

申请号：US14609082

申请日：2015-01-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sung-Li Wang ,  Ding-Kang Shih ,  Chin-Hsiang Lin ,  Sey-Ping Sun ,  Clement Hsingjen Wann

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/306 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/66636 ,  H01L21/02164 ,  H01L21/02172 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02614 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28525 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L29/0642 ,  H01L29/0847 ,  H01L29/41758 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7378 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a semiconductor layer on the sidewalls and bottom of the opening; a dielectric layer on the semiconductor layer; and a metal layer filling an opening of the dielectric layer.

Abstract translation: 本发明涉及半导体器件的接触结构。 用于半导体器件的接触结构的示例性结构包括：基底，其包括主表面和主表面下方的沟槽; 填充沟槽的应变材料，其中应变材料的晶格常数不同于衬底的晶格常数; 在所述应变材料上具有开口的层间介电层（ILD）层，其中所述开口包括电介质侧壁和应变材料底部; 在开口的侧壁和底部上的半导体层; 半导体层上的介电层; 以及填充介电层的开口的金属层。