公开(公告)号：US10002877B2

公开(公告)日：2018-06-19

申请号：US15448697

申请日：2017-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jintaek Park ,  Youngwoo Park ,  Jaeduk Lee

IPC: G11C5/02 ,  H01L27/11573 ,  G11C16/04 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/1157

CPC classification number: H01L27/11573 ,  G11C5/02 ,  G11C5/025 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: A three-dimensional (3D) semiconductor memory device includes a CMOS circuit structure including a plurality of column blocks each comprising a plurality of page buffer circuits, and a lower wiring structure and a memory structure sequentially stacked over the CMOS circuit structure. The memory structure overlaps a first circuit region of the CMOS circuit structure and does not overlap a second circuit region of the CMOS circuit structure, and the plurality of column blocks are contained within the first circuit region of the CMOS circuit structure.

公开(公告)号：US09865685B2

公开(公告)日：2018-01-09

申请号：US15403440

申请日：2017-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaesung Sim ,  Youngwoo Park

IPC: H01L29/10 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/267 ,  H01L29/161 ,  H01L29/165 ,  H01L29/788 ,  H01L29/16

CPC classification number: H04L49/70 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/267 ,  H01L29/7883 ,  H04L45/16 ,  H04L49/201 ,  H04L49/3009

Abstract: Semiconductor memory devices and methods of forming the semiconductor devices may be provided. The semiconductor memory devices may include a channel portion of an active pillar that may be formed of a semiconductor material having a charge mobility greater than a charge mobility of silicon. The semiconductor devices may also include a non-channel portion of the active pillar including a semiconductor material having a high silicon content.

公开(公告)号：US09768018B2

公开(公告)日：2017-09-19

申请号：US15097369

申请日：2016-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： YuJeong Seo ,  JinTaek Park ,  Youngwoo Park

IPC: H01L21/20 ,  H01L21/02 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/10 ,  H01L29/16 ,  H01L29/792

CPC classification number: H01L21/02672 ,  H01L21/02532 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/7923 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The inventive concepts provide semiconductor devices and methods of fabricating the same. According to the method, sub-stack structures having a predetermined height and active holes are repeatedly stacked. Thus, cell dispersion may be improved, and various errors such as a not-open error caused in an etching process may be prevented. A grain size of an active pillar used as channels may be increased or maximized using a metal induced lateral crystallization method, so that a cell current may be improved. A formation position of a metal silicide layer including a crystallization inducing metal may be controlled such that a concentration grade of the crystallization inducing metal may be controlled depending on a position within the active pillar.

公开(公告)号：US09142563B2

公开(公告)日：2015-09-22

申请号：US14599621

申请日：2015-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Il Chang ,  Youngwoo Park ,  Jaegoo Lee

IPC: H01L29/792 ,  H01L27/115 ,  H01L21/311

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/42324 ,  H01L29/4234

Abstract: A 3D semiconductor device includes an electrode structure has electrodes stacked on a substrate, semiconductor patterns penetrating the electrode structure, charge storing patterns interposed between the semiconductor patterns and the electrode structure, and blocking insulating patterns interposed between the charge storing patterns and the electrode structure. Each of the blocking insulating patterns surrounds the semiconductor patterns, and the charge storing patterns are horizontally spaced from each other and configured in such a way as to each be disposed around a respective one of the semiconductor patterns. Also, each of the charge storing patterns includes a plurality of horizontal segments, each interposed between vertically adjacent ones of the electrodes.

公开(公告)号：US10229927B2

公开(公告)日：2019-03-12

申请号：US14725476

申请日：2015-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dohyun Lee ,  Jaegoo Lee ,  Young-Jin Kwon ,  Youngwoo Park ,  Jaeduk Lee

IPC: H01L27/115 ,  H01L27/11582 ,  H01L29/10 ,  H01L29/792 ,  H01L27/1157

Abstract: A semiconductor device includes a lower stack structure including lower gate electrodes and lower insulating layers that are alternately and repeatedly stacked on a substrate. The semiconductor device includes an upper stack structure including upper gate electrodes and upper insulating layers that are alternately and repeatedly stacked on the lower stack structure. A lower channel structure penetrates the lower stack structure. An upper channel structure penetrates and is connected to the upper stack structure. A lower vertical insulator is disposed between the lower stack structure and the lower channel structure. The lower channel structure includes a first vertical semiconductor pattern connected to the substrate, and a first connecting semiconductor pattern disposed on the first vertical semiconductor pattern. The upper channel structure includes a second vertical semiconductor pattern electrically connected to the first vertical semiconductor pattern with the first connecting semiconductor pattern disposed therebetween.

公开(公告)号：US09847346B2

公开(公告)日：2017-12-19

申请号：US15259941

申请日：2016-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun Lee ,  Heonkyu Lee ,  Shinhwan Kang ,  Youngwoo Park

IPC: H01L29/49 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11519

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

Abstract: A three-dimensional semiconductor memory device includes a stack on a substrate including electrodes vertically stacked on a substrate, lower insulating patterns disposed between the stack and the substrate, the lower insulating patterns being adjacent to both sidewalls of the stack and being spaced apart from each other, a plurality of vertical structures penetrating the stack and being connected to the substrate, and a data storing pattern between the stack and the vertical structures, the data storing pattern including a portion disposed between the lowermost one of the electrodes and the substrate.

公开(公告)号：US09768193B2

公开(公告)日：2017-09-19

申请号：US15141263

申请日：2016-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaegoo Lee ,  Youngwoo Park

IPC: H01L21/8238 ,  H01L21/336 ,  H01L29/76 ,  H01L29/06 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11548 ,  H01L27/11575

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional (3D) semiconductor device includes a stack of conductive layers spaced from each other in a vertical direction, the stack having a staircase-shaped section in a connection region, and ends of the conductive layers constituting treads of the staircase-shaped section, respectively. The 3D semiconductor device further includes buffer patterns disposed on and protruding above the respective ends of the conductive layers, an interconnection structure disposed above the stack and including conductive lines, and contact plugs extending vertically between the conductive lines and the buffer patterns and electrically connected to the conductive layers of the stack via the buffer patterns.

公开(公告)号：US09385139B2

公开(公告)日：2016-07-05

申请号：US14753713

申请日：2015-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Il Chang ,  Youngwoo Park ,  Jaegoo Lee

IPC: H01L29/792 ,  H01L27/115 ,  H01L21/28 ,  H01L21/311 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/42324 ,  H01L29/4234

Abstract: A 3D semiconductor device includes an electrode structure has electrodes stacked on a substrate, semiconductor patterns penetrating the electrode structure, charge storing patterns interposed between the semiconductor patterns and the electrode structure, and blocking insulating patterns interposed between the charge storing patterns and the electrode structure. Each of the blocking insulating patterns surrounds the semiconductor patterns, and the charge storing patterns are horizontally spaced from each other and configured in such a way as to each be disposed around a respective one of the semiconductor patterns. Also, each of the charge storing patterns includes a plurality of horizontal segments, each interposed between vertically adjacent ones of the electrodes.

公开(公告)号：US09012320B2

公开(公告)日：2015-04-21

申请号：US14258436

申请日：2014-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaegoo Lee ,  Kil-Su Jeong ,  Hansoo Kim ,  Youngwoo Park

IPC: H01L27/115

CPC classification number: H01L23/52 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Example embodiments relate to a three-dimensional semiconductor memory device including an electrode structure on a substrate, the electrode structure including at least one conductive pattern on a lower electrode, and a semiconductor pattern extending through the electrode structure to the substrate. A vertical insulating layer may be between the semiconductor pattern and the electrode structure, and a lower insulating layer may be between the lower electrode and the substrate. The lower insulating layer may be between a bottom surface of the vertical insulating layer and a top surface of the substrate. Example embodiments related to methods for fabricating the foregoing three-dimensional semiconductor memory device.

Abstract translation: 示例实施例涉及一种三维半导体存储器件，其包括在衬底上的电极结构，该电极结构包括在下电极上的至少一个导电图案，以及半导体图案，其延伸穿过该电极结构到该衬底。 垂直绝缘层可以在半导体图案和电极结构之间，下绝缘层可以位于下电极和衬底之间。 下绝缘层可以在垂直绝缘层的底表面和基板的顶表面之间。 与制造上述三维半导体存储器件的方法相关的示例实施例。