公开(公告)号：US09768018B2

公开(公告)日：2017-09-19

申请号：US15097369

申请日：2016-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： YuJeong Seo ,  JinTaek Park ,  Youngwoo Park

IPC: H01L21/20 ,  H01L21/02 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/10 ,  H01L29/16 ,  H01L29/792

CPC classification number: H01L21/02672 ,  H01L21/02532 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/7923 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The inventive concepts provide semiconductor devices and methods of fabricating the same. According to the method, sub-stack structures having a predetermined height and active holes are repeatedly stacked. Thus, cell dispersion may be improved, and various errors such as a not-open error caused in an etching process may be prevented. A grain size of an active pillar used as channels may be increased or maximized using a metal induced lateral crystallization method, so that a cell current may be improved. A formation position of a metal silicide layer including a crystallization inducing metal may be controlled such that a concentration grade of the crystallization inducing metal may be controlled depending on a position within the active pillar.