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公开(公告)号:US11710741B2
公开(公告)日:2023-07-25
申请号:US17243943
申请日:2021-04-29
Applicant: Samsung Electronics Co., Ltd.
Inventor: Chang Woo Noh , Myung Gil Kang , Geum Jong Bae , Dong Il Bae , Jung Gil Yang , Sang Hoon Lee
IPC: H01L27/092 , H01L29/78 , H01L29/66 , H01L21/033 , H01L21/8238 , H01L29/10 , H01L29/08
CPC classification number: H01L27/0924 , H01L21/0337 , H01L21/823821 , H01L21/823828 , H01L21/823864 , H01L21/823871 , H01L29/0847 , H01L29/1033 , H01L29/6656 , H01L29/6681 , H01L29/66545 , H01L29/785 , H01L2029/7858
Abstract: Semiconductor devices are provided. The semiconductor devices may include a first wire pattern extending in a first direction on a substrate and a second wire pattern on the first wire pattern. The second wire pattern may be spaced apart from the first wire pattern and extends in the first direction. The semiconductor devices may also include a first gate structure at least partially surrounding the first wire pattern and the second wire pattern, a second gate structure spaced apart from the first gate structure in the first direction, a first source/drain region between the first gate structure and the second gate structure, a first spacer between a bottom surface of the first source/drain region and the substrate, a first source/drain contact on the first source/drain region, and a second spacer between the first source/drain contact and the first gate structure.
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公开(公告)号:US11640973B2
公开(公告)日:2023-05-02
申请号:US17508197
申请日:2021-10-22
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung Gil Yang , Dong Il Bae , Chang Woo Sohn , Seung Min Song , Dong Hun Lee
IPC: H01L29/06 , H01L21/8234 , H01L29/66 , H01L29/08 , H01L21/8238 , H01L27/088 , H01L29/165 , H01L29/10 , H01L27/092 , H01L27/02 , H01L29/423 , H01L29/78 , H01L29/786
Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.
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公开(公告)号:US11164943B2
公开(公告)日:2021-11-02
申请号:US16928439
申请日:2020-07-14
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung Gil Yang , Dong Il Bae , Chang Woo Sohn , Seung Min Song , Dong Hun Lee
IPC: H01L29/06 , H01L29/66 , H01L29/08 , H01L21/8238 , H01L21/8234 , H01L27/088 , H01L29/165 , H01L29/10 , H01L27/092 , H01L27/02 , H01L29/423 , H01L29/78 , H01L29/786
Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.
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公开(公告)号:US10756179B2
公开(公告)日:2020-08-25
申请号:US16423641
申请日:2019-05-28
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung Gil Yang , Dong Il Bae , Chang Woo Sohn , Seung Min Song , Dong Hun Lee
IPC: H01L29/06 , H01L21/8234 , H01L29/66 , H01L29/08 , H01L21/8238 , H01L27/088 , H01L29/165 , H01L29/10 , H01L27/092 , H01L27/02 , H01L29/423 , H01L29/78 , H01L29/786
Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.
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公开(公告)号:US10749030B2
公开(公告)日:2020-08-18
申请号:US16018121
申请日:2018-06-26
Applicant: Samsung Electronics Co., Ltd.
Inventor: Soojin Jeong , Dong Il Bae , Geumjong Bae , Seungmin Song , Junggil Yang
IPC: H01L29/78 , H01L29/06 , H01L29/423 , H01L27/092 , H01L29/08 , H01L29/786 , H01L29/66 , H01L21/8238 , H01L27/06
Abstract: A semiconductor device may include first and second channel patterns on a substrate, first and second source/drain patterns in contact respectively with the first and second channel patterns, and first and second gate electrodes respectively overlapping the first and second channel patterns. The first gate electrode may include a first segment between first and second semiconductor patterns of the first channel pattern. The first segment may include a first convex portion protruding toward the first source/drain pattern. The second gate electrode may include a second segment between third and fourth semiconductor patterns of the second channel pattern. The second segment may include a concave portion recessed toward a center of the second segment.
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公开(公告)号:US20200091152A1
公开(公告)日:2020-03-19
申请号:US16405174
申请日:2019-05-07
Applicant: Samsung Electronics Co., Ltd.
Inventor: Chang Woo Noh , Myung Gil Kang , Geum Jong Bae , Dong Il Bae , Jung Gil Yang , Sang Hoon Lee
IPC: H01L27/092 , H01L29/78 , H01L29/66 , H01L21/033 , H01L21/8238 , H01L29/10 , H01L29/08
Abstract: Semiconductor devices are provided. The semiconductor devices may include a first wire pattern extending in a first direction on a substrate and a second wire pattern on the first wire pattern. The second wire pattern may be spaced apart from the first wire pattern and extends in the first direction. The semiconductor devices may also include a first gate structure at least partially surrounding the first wire pattern and the second wire pattern, a second gate structure spaced apart from the first gate structure in the first direction, a first source/drain region between the first gate structure and the second gate structure, a first spacer between a bottom surface of the first source/drain region and the substrate, a first source/drain contact on the first source/drain region, and a second spacer between the first source/drain contact and the first gate structure.
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公开(公告)号:US20190393315A1
公开(公告)日:2019-12-26
申请号:US16205851
申请日:2018-11-30
Applicant: Samsung Electronics Co., Ltd.
Inventor: Chang Woo NOH , Seung Min Song , Geum Jong Bae , Dong Il Bae
IPC: H01L29/417 , H01L29/66 , H01L29/78 , H01L21/768 , H01L29/06
Abstract: A semiconductor device including a fin field effect transistor (fin-FET) includes active fins disposed on a substrate, isolation layers on both sides of the active fins, a gate structure formed to cross the active fins and the isolation layers, source/drain regions on the active fins on sidewalls of the gate structure, a first interlayer insulating layer on the isolation layers in contact with portions of the sidewalls of the gate structure and portions of surfaces of the source/drain regions, an etch stop layer configured to overlap the first interlayer insulating layer, the sidewalls of the gate structure, and the source/drain regions, and contact plugs formed to pass through the etch stop layer to contact the source/drain regions. The source/drain regions have main growth portions in contact with upper surfaces of the active fins.
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公开(公告)号:US10128379B2
公开(公告)日:2018-11-13
申请号:US15647903
申请日:2017-07-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Seung Min Song , Woo Seok Park , Geum Jong Bae , Dong Il Bae , Jung Gil Yang
IPC: H01L29/786 , H01L29/06 , H01L29/423 , H01L29/66 , H01L21/02
Abstract: A semiconductor device includes a substrate; protruding portions extending in parallel to each other on the substrate; nanowires provided on the protruding portions and separated from each other; gate electrodes provided on the substrate and surrounding the nanowires; source/drain regions provided on the protruding portions and sides of each of the gate electrodes, the source/drain regions being in contact with the nanowires; and first voids provided between the source/drain regions and the protruding portions.
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公开(公告)号:US10090328B2
公开(公告)日:2018-10-02
申请号:US15429719
申请日:2017-02-10
Applicant: Samsung Electronics Co., Ltd.
Inventor: Junggil Yang , Dong Il Bae , Geumjong Bae , Seungmin Song , Jongho Lee
Abstract: A semiconductor device includes an insulating layer on a substrate, a first channel pattern on the insulating layer and contacting the insulating layer, second channel patterns on the first channel pattern and being horizontally spaced apart from each other, a gate pattern on the insulating layer and surrounding the second channel patterns, and a source/drain pattern between the second channel patterns.
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公开(公告)号:US09953883B2
公开(公告)日:2018-04-24
申请号:US15415012
申请日:2017-01-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Mirco Cantoro , Maria Toledano Luque , Yeoncheol Heo , Dong Il Bae
IPC: H01L21/8238 , H01L21/02 , H01L21/306 , H01L21/308 , H01L21/311 , H01L27/092 , H01L27/11 , H01L29/08 , H01L29/165 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/06
CPC classification number: H01L21/823821 , H01L21/02167 , H01L21/0217 , H01L21/02233 , H01L21/02255 , H01L21/02532 , H01L21/02612 , H01L21/02639 , H01L21/30604 , H01L21/308 , H01L21/31111 , H01L21/823807 , H01L27/092 , H01L27/0924 , H01L27/1104 , H01L29/0649 , H01L29/0847 , H01L29/165 , H01L29/42376 , H01L29/66636 , H01L29/7848
Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor layer on a substrate, the semiconductor layer including a first semiconductor material and a second semiconductor material, patterning the semiconductor layer to form a preliminary active pattern, oxidizing at least two sidewalls of the preliminary active pattern to form an oxide layer on each of the at least two sidewalls of the preliminary active pattern, at least two upper patterns and a semiconductor pattern being formed in the preliminary active pattern when the oxide layers are formed, the semiconductor pattern being disposed between the at least two upper patterns, and removing the semiconductor pattern to form an active pattern, the active pattern including the at least two upper patterns. A concentration of the second semiconductor material in each of the at least two upper patterns is higher than a concentration of the second semiconductor material in the semiconductor pattern.
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