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    Selectively recessing trench isolation in three-dimensional (3D) transistors to vary channel structure exposures from trench isolation to control drive strength
    31.
    发明授权
    Selectively recessing trench isolation in three-dimensional (3D) transistors to vary channel structure exposures from trench isolation to control drive strength 有权

    公开(公告)号：US10109646B1

    公开(公告)日：2018-10-23

    申请号：US15613656

    申请日：2017-06-05

    Applicant: QUALCOMM Incorporated

    Inventor： Mustafa Badaroglu

    IPC: H01L27/118

    Abstract: Selectively recessing trench isolation in three-dimensional (3D) transistors to vary channel structure exposures from trench isolation to control drive strength is disclosed. The ability to vary the exposures of channel structures in 3D transistors from trench isolation allows the drive strengths of the 3D transistors to be varied. Varying the drive strengths of 3D transistors may be advantageous in certain circuit applications to reduce power consumption and/or control drive strength ratios between transistors, as examples. In this regard, in exemplary aspects disclosed herein, during the fabrication of 3D transistors, a trench isolation material is disposed adjacent to channel structures formed from a substrate. The amount of trench isolation material disposed adjacent to each channel structure determines the amount of channel structure surface area exposed to a gate. The amount of channel structure surface area of the 3D transistor exposed to the gate affects the drive strength of the 3D transistor.

    MINIMUM TRACK STANDARD CELL CIRCUITS FOR REDUCED AREA
    34.
    发明申请
    MINIMUM TRACK STANDARD CELL CIRCUITS FOR REDUCED AREA 有权

    公开(公告)号：US20180076189A1

    公开(公告)日：2018-03-15

    申请号：US15266523

    申请日：2016-09-15

    Applicant: QUALCOMM Incorporated

    Inventor： Jeffrey Junhao Xu ,  Mustafa Badaroglu ,  Da Yang

    IPC: H01L27/02 ,  H01L29/423 ,  G06F17/50

    CPC classification number: H01L27/0207 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  H01L27/11807 ,  H01L29/4232 ,  H01L2027/11811

    Abstract: Minimum track standard cell circuits for reduced area are provided. In one aspect, a minimum track standard cell circuit employs a first high aspect ratio voltage rail disposed over a first one-half track and configured to provide a first voltage (e.g., VDD) to the minimum track standard cell circuit. A second high aspect ratio voltage rail is disposed over a second one-half track substantially parallel to the first high aspect ratio voltage rail. The second high aspect ratio voltage rail is configured to provide a second voltage less than the first voltage (e.g., VSS) to the minimum track standard cell circuit. The minimum track standard cell circuit employs multiple tracks disposed between the first and second one-half tracks. The number of tracks can be limited based on particular factors. Minimizing tracks reduces area compared to conventional standard cell circuits.

    Reduced height M1 metal lines for local on-chip routing
    38.
    发明授权
    Reduced height M1 metal lines for local on-chip routing 有权
    降低M1金属线路用于本地片上路由

    公开(公告)号：US09349686B2

    公开(公告)日：2016-05-24

    申请号：US14206360

    申请日：2014-03-12

    Applicant: QUALCOMM Incorporated

    Inventor： Stanley Seungchul Song ,  Choh Fei Yeap ,  Zhongze Wang ,  Niladri Mojumder ,  Mustafa Badaroglu

    IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768

    CPC classification number: H01L21/76879 ,  H01L21/02167 ,  H01L21/76829 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Systems and methods are directed to an integrated circuit comprising a reduced height M1 metal line formed of an exemplary material with lower mean free path than Copper, for local routing of on-chip circuit elements of the integrated circuit, wherein the height of the reduced height M1 metal line is lower than a minimum allowed or allowable height of a conventional M1 metal line formed of Copper. The exemplary materials for forming the reduced height M1 metal line include Tungsten (W), Molybdenum (Mo), and Ruthenium (Ru), wherein these exemplary materials also exhibit lower capacitance and lower RC delays than Copper, while providing high electromigration reliability.

    Abstract translation: 系统和方法涉及一种集成电路，其包括由具有比铜的平均自由路径更低的示例性材料形成的减小的高度M1金属线，用于集成电路的片上电路元件的局部布线，其中降低的高度 M1金属线低于由铜形成的常规M1金属线的最小允许或允许的高度。 用于形成还原高度M1金属线的示例性材料包括钨（W），钼（Mo）和钌（Ru），其中这些示例性材料还具有比铜更低的电容和更低的RC延迟，同时提供高电迁移可靠性。

    DIGITAL COMPUTE-IN-MEMORY (DCIM) BIT CELL CIRCUIT LAYOUTS AND DCIM ARRAYS FOR MULTIPLE OPERATIONS PER COLUMN
    39.
    发明申请
    DIGITAL COMPUTE-IN-MEMORY (DCIM) BIT CELL CIRCUIT LAYOUTS AND DCIM ARRAYS FOR MULTIPLE OPERATIONS PER COLUMN 有权

    公开(公告)号：US20220392524A1

    公开(公告)日：2022-12-08

    申请号：US17341797

    申请日：2021-06-08

    Applicant: QUALCOMM Incorporated

    Inventor： Xiaonan Chen ,  Zhongze Wang ,  Yandong Gao ,  Mustafa Badaroglu

    IPC: G11C11/419 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/4091 ,  G06N3/063 ,  G06F7/544

    Abstract: Digital compute-in-memory (DCIM) bit cell circuit layouts and DCIM array circuits for multiple operations per column are disclosed. A DCIM bit cell array circuit including DCIM bit cell circuits comprising exemplary DCIM bit cell circuit layouts disposed in columns is configured to evaluate the results of multiple multiply operations per clock cycle. The DCIM bit cell circuits in the DCIM bit cell circuit layouts each couples to one of a plurality of column output lines in a column. In this regard, in each cycle of a system clock, each of the plurality of column output lines receives a result of a multiply operation of a DCIM bit cell circuit coupled to the column output line. The DCIM bit cell array circuit includes digital sense amplifiers coupled to each of the plurality of column output lines to reliably evaluate a result of a plurality of multiply operations per cycle.

    Hybrid metallization interconnects for power distribution and signaling
    40.
    发明授权
    Hybrid metallization interconnects for power distribution and signaling 有权

    公开(公告)号：US11121075B2

    公开(公告)日：2021-09-14

    申请号：US15933581

    申请日：2018-03-23

    Applicant: QUALCOMM Incorporated

    Inventor： Mustafa Badaroglu ,  Kern Rim

    IPC: H01L23/522 ,  H01L23/528 ,  H01L23/50 ,  H01L23/532

    Abstract: Aspects of the disclosure are directed to an integrated circuit. The integrated circuit may include a signaling interconnect having a narrow trench disposed within a metallization layer, and a power rail having a wide trench disposed within the metallization layer, wherein the signaling interconnect comprises non-copper material and the power rail comprises copper. The non-copper material may include at least one of ruthenium (Ru), tungsten (W), aluminum (Al), and cobalt (Co). The signaling interconnect and power rail may be processed in a common chemical mechanical polishing step and have approximately the same trench depth. A metal cap may be deposited on top of the power rail.

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