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公开(公告)号：US20240361370A1
公开(公告)日：2024-10-31
申请号：US18767126
申请日：2024-07-09
IPC分类号： G01R27/26 , G01R31/26 , G01R31/28 , H03K19/094
CPC分类号： G01R27/2605 , G01R31/2639 , G01R31/2841 , H03K19/094
摘要： Systems and methods are described herein for charge-based capacitor measurement. The system includes a first pseudo-inverter circuit and a second pseudo-inverter circuit. The system also includes a control circuit coupled between the first inverter circuit and the second inverter circuit. The control circuit is configured to generate independent and non-overlapping control signals for the first pseudo-inverter circuit and the second pseudo-inverter circuit. A shielding metal is coupled to the first pseudo-inverter circuit, the second pseudo-inverter circuit, and the control circuit. The shielding metal is configured to dissipate parasitic capacitance of at least one of the first pseudo-inverter circuit or the second pseudo-inverter circuit. A device under test is coupled to each of the first inverter circuit and the second inverter circuit.
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公开(公告)号：US20240360548A1
公开(公告)日：2024-10-31
申请号：US18769943
申请日：2024-07-11
发明人： Chi-Cheng HUNG , Pei-Wen WU , Yu-Sheng WANG , Pei-Shan CHANG
CPC分类号： C23C16/06 , C23C16/0281 , H01L21/02425 , H01L21/0332 , H01L29/34 , H01L29/66795
摘要： In some implementations, one or more semiconductor processing tools may deposit cobalt material within a cavity of the semiconductor device. The one or more semiconductor processing tools may polish an upper surface of the cobalt material. The one or more semiconductor processing tools may perform a hydrogen soak on the semiconductor device. The one or more semiconductor processing tools may deposit tungsten material onto the upper surface of the cobalt material.
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公开(公告)号：US20240359194A1
公开(公告)日：2024-10-31
申请号：US18769077
申请日：2024-07-10
发明人： Channing CHAN , Kuo-Shu TSENG , Chun-Chih LIN
CPC分类号： B05B1/185 , B05B1/30 , B05B13/0431 , B08B3/024 , B08B3/08 , H01L21/67023 , H01L21/67051 , H01L21/6708 , B08B3/10
摘要： A system for dispensing a liquid includes a conduit, the conduit being configured to convey the liquid; a dispensing tip fluidically coupled to the conduit; and a movable arm, the movable arm being configured to change a position of the dispensing tip relative to a workpiece to which the liquid is dispensed. The dispensing tip includes a first section having a liquid-containing wall and a septum, the septum divides the first section into at least a first liquid passage and a second liquid passage, and the septum is disposed to contact the liquid in each of the at least first liquid passage and second liquid passage during dispensing of the liquid to the workpiece.
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公开(公告)号：US12133470B2
公开(公告)日：2024-10-29
申请号：US18059073
申请日：2022-11-28
摘要： The present disclosure provides a semiconductor structure, including an Nth metal layer over a transistor region, where N is a natural number, and a bottom electrode over the Nth metal layer. The bottom electrode comprises a bottom portion having a first width, disposed in a bottom electrode via (BEVA), the first width being measured at a top surface of the BEVA, and an upper portion having a second width, disposed over the bottom portion. The semiconductor structure also includes a magnetic tunneling junction (MTJ) layer having a third width, disposed over the upper portion, a top electrode over the MTJ layer and an (N+1)th metal layer over the top electrode. The first width is greater than the third width.
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公开(公告)号：US12133390B2
公开(公告)日：2024-10-29
申请号：US18170557
申请日：2023-02-17
发明人： Chao-I Wu , Yu-Ming Lin , Sai-Hooi Yeong
CPC分类号： H10B51/20 , H01L29/40111 , H01L29/517 , H01L29/518 , H10B41/23 , H10B51/00 , H10B51/10 , H10B51/30
摘要： Provided are a memory device and a method of forming the same. The memory device includes a substrate, a layer stack, and a plurality of composite pillar structures. The layer stack is disposed on the substrate. The layer stack includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The composite pillar structures respectively penetrate through the layer stack. Each composite pillar structure includes a dielectric pillar; a pair of conductive pillars penetrating through the dielectric pillar and electrically isolated from each other through a portion of the dielectric pillar; a channel layer covering both sides of the dielectric pillar and the pair of conductive pillars; a ferroelectric layer disposed between the channel layer and the layer stack; and a buffer layer disposed between the channel layer and the ferroelectric layer.
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公开(公告)号：US12132247B2
公开(公告)日：2024-10-29
申请号：US17874291
申请日：2022-07-27
发明人： Yen-Ping Wang , Chun-Lin Lu , Han-Ping Pu , Kai-Chiang Wu , Chung-Yi Hsu
CPC分类号： H01Q1/2283 , H01L23/31 , H01L23/66 , H01Q9/0407
摘要： A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes: patch antennas, encapsulated by a first encapsulant; a device die, vertically spaced apart from the patch antennas, and electrically coupled to the patch antennas; and at least one redistribution structure, disposed between the patch antennas and the device die, and including electromagnetic bandgap (EBG) structures laterally surrounding each of the patch antennas.
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公开(公告)号：US12132096B2
公开(公告)日：2024-10-29
申请号：US18360110
申请日：2023-07-27
发明人： Xusheng Wu , Chang-Miao Liu , Huiling Shang
IPC分类号： H01L21/82 , H01L21/265 , H01L21/28 , H01L21/8234 , H01L27/088 , H01L29/423 , H01L29/49 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66545 , H01L21/26586 , H01L21/28008 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L21/823468 , H01L27/0886 , H01L29/4236 , H01L29/49 , H01L29/6653 , H01L29/6656 , H01L29/66795 , H01L29/785
摘要： A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a gate stack over the substrate. The semiconductor device structure also includes a spacer element over a sidewall of the gate stack. The spacer element is doped with a dopant, and the dopant reduces a dielectric constant of the spacer element. The spacer element has a first atomic concentration of the dopant near an inner surface of the spacer element adjacent to the gate stack. The spacer element has a second atomic concentration of the dopant near an outer surface of the spacer element. The first atomic concentration of the dopant is different than the second atomic concentration of the dopant.
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公开(公告)号：US12132079B2
公开(公告)日：2024-10-29
申请号：US18392379
申请日：2023-12-21
发明人： Kuan-Kan Hu , Han-De Chen , Ku-Feng Yang , Chen-Fong Tsai , Chi On Chui , Szuya Liao
IPC分类号： H01L29/06 , H01L21/8238 , H01L25/07 , H01L27/092 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L29/0653 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L25/074 , H01L27/092 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/78696
摘要： Bonding and isolation techniques for stacked device structures are disclosed herein. An exemplary method includes forming a first insulation layer on a first device component, forming a second insulation layer on a second device component, and bonding the first insulation layer and the second insulation layer. The bonding provides a stacked structure that includes the first device component over the second device component, and an isolation structure (formed by the first insulation layer bonded to the second insulation layer) therebetween. The isolation structure includes a first portion having a first composition and a second portion having a second composition different than the first composition. The method further includes processing the stacked structure to form a first device disposed over a second device, where the isolation structure separates the first device and the second device. The first insulation layer and the second insulation layer may include the same or different materials.
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公开(公告)号：US12132075B2
公开(公告)日：2024-10-29
申请号：US17412456
申请日：2021-08-26
发明人： Hung-Wen Hsu , Jiech-Fun Lu , Li-Weng Chang
IPC分类号： H01L29/06 , H01L21/311 , H01L21/3213 , H01L23/522 , H01L23/528 , H01L27/06 , H01L49/02
CPC分类号： H01L28/20 , H01L21/31116 , H01L21/32134 , H01L23/5226 , H01L23/528 , H01L27/0688
摘要： Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a substrate. A resistor overlies the substrate. The resistor comprises a resistive structure overlying the substrate. The resistor also comprises a conductive contact overlying and electrically coupled to the resistive structure. A capping structure is disposed over the conductive contact, wherein the capping structure extends laterally over an upper surface of the conductive contact and vertically along a first sidewall of the conductive contact, such that a lower surface of the capping structure is disposed below a lower surface of the conductive contact.
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公开(公告)号：US12132051B2
公开(公告)日：2024-10-29
申请号：US17875277
申请日：2022-07-27
IPC分类号： H01L29/06 , H01L21/8238 , H01L27/092 , H01L29/51
CPC分类号： H01L27/0924 , H01L21/823821 , H01L21/823857 , H01L29/517
摘要： A gate structure of a field effect transistor includes a first gate dielectric layer, a second gate dielectric layer, and one or more conductive layers disposed over the first gate dielectric layer and the second gate dielectric layer. The first gate dielectric layer is separated from the second gate dielectric layer by a gap filled with a diffusion blocking layer.
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