公开(公告)号：US20240304658A1

公开(公告)日：2024-09-12

申请号：US18664402

申请日：2024-05-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun-Tsung Kuo ,  Jiech-Fun Lu

IPC分类号： H01L21/768

CPC分类号： H01L28/24 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877

摘要： Various embodiments of the present disclosure are directed towards an integrated chip including a resistor layer over a substrate. An isolation structure contacts a first pair of opposing sidewalls of the first resistor layer. The isolation structure includes a body structure and a liner layer disposed on opposing sidewalls of the body structure.

公开(公告)号：US11769778B2

公开(公告)日：2023-09-26

申请号：US17406297

申请日：2021-08-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsun-Kai Tsao ,  Jiech-Fun Lu ,  Shih-Pei Chou ,  Tzu-Ming Wang

IPC分类号： H01L27/146

CPC分类号： H01L27/14625 ,  H01L27/14612 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14685 ,  H01L27/14689 ,  H01L27/1463 ,  H01L27/14621 ,  H01L27/14627

摘要： Various embodiments of the present disclosure are directed towards a method for forming an image sensor. The method includes forming a photodetector in a substrate. A lower interconnect portion of an interconnect structure is formed over the photodetector. A removal process is performed to define a first opening overlying the photodetector in the lower interconnect portion. A lower etch stop layer is formed lining the first opening. The lower etch stop layer has a U-shape in the first opening. An upper interconnect portion of the interconnect structure is formed over the lower etch stop layer. A light pipe structure is formed overlying the photodetector. The U-shape of the lower etch stop layer extends continuously along sidewalls and a bottom surface of the light pipe structure.

公开(公告)号：US20220149147A1

公开(公告)日：2022-05-12

申请号：US17579129

申请日：2022-01-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun-Tsung Kuo ,  Jiech-Fun Lu

IPC分类号： H01L49/02 ,  H01L21/768

摘要： Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes depositing a resistive layer over a substrate. A conductive structure is formed over the resistive layer. A first etch process is performed on the resistive layer to define a resistor segment of the resistive layer and a peripheral region of the resistive layer. The resistor segment is laterally separated from the peripheral region of the resistive layer. The peripheral region continuously laterally wraps around an outer perimeter of the resistor segment.

公开(公告)号：US20220077305A1

公开(公告)日：2022-03-10

申请号：US17528654

申请日：2021-11-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun-Tsung Kuo ,  Jiech-Fun Lu

IPC分类号： H01L29/737 ,  H01L29/66 ,  H01L29/165 ,  H01L21/311 ,  H01L21/02 ,  H01L29/08 ,  H01L21/033 ,  H01L29/10

摘要： Various embodiments of the present disclosure are directed towards a method for forming a bipolar junction transistor (BJT). A dielectric film is deposited over a substrate and comprises a lower dielectric layer, an upper dielectric layer, and an intermediate dielectric layer between the lower and upper dielectric layers. A first semiconductor layer is deposited over the dielectric film and is subsequently patterned to form an opening exposing the dielectric film. A first etch is performed into the upper dielectric layer through the opening to extend the opening to the intermediate dielectric layer. Further, the first etch stops on the intermediate dielectric layer and laterally undercuts the first semiconductor layer. Additional etches are performed to extend the opening to the substrate. A lower base structure and an emitter are formed stacked in and filling the opening, and the first semiconductor layer is patterned to form an upper base structure.

公开(公告)号：US10361234B2

公开(公告)日：2019-07-23

申请号：US15944069

申请日：2018-04-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih Pei Chou ,  Hung-Wen Hsu ,  Ching-Chung Su ,  Chun-Han Tsao ,  Chia-Chieh Lin ,  Shu-Ting Tsai ,  Jiech-Fun Lu ,  Shih-Chang Liu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

IPC分类号： H01L27/146 ,  H01L23/48 ,  H01L25/065 ,  H01L21/768 ,  H01L25/00 ,  H01L21/683 ,  H01L25/16

摘要： An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.

公开(公告)号：US10128113B2

公开(公告)日：2018-11-13

申请号：US14993468

申请日：2016-01-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Shih-Pei Chou ,  Chen-Fa Lu ,  Jiech-Fun Lu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

IPC分类号： H01L21/033 ,  H01L21/762 ,  H01L21/32 ,  H01L21/768 ,  H01L23/48

摘要： A semiconductor structure comprises a substrate comprising an interlayer dielectric (ILD) and a silicon layer disposed over the ILD, wherein the ILD comprises a conductive structure disposed therein, a dielectric layer disposed over the silicon layer, and a conductive plug electrically connected with the conductive structure and extended from the dielectric layer through the silicon layer to the ILD, wherein the conductive plug has a length running from the dielectric layer to the ILD and a width substantially consistent along the length.

公开(公告)号：US09984918B2

公开(公告)日：2018-05-29

申请号：US15088126

申请日：2016-04-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Ching-Chung Su ,  Jiech-Fun Lu ,  Jian Wu ,  Che-Hsiang Hsueh ,  Ming-Chi Wu ,  Chi-Yuan Wen ,  Chun-Chieh Fang ,  Yu-Lung Yeh

IPC分类号： H01L21/764 ,  H01L21/762

CPC分类号： H01L21/764 ,  H01L21/3083 ,  H01L21/76232

摘要： A semiconductor structure includes a semiconductive substrate including a first surface and a second surface opposite to the first surface, a shallow trench isolation (STI) including a first portion at least partially disposed within the semiconductive substrate and tapered from the first surface towards the second surface, and a second portion disposed inside the semiconductive substrate, coupled with the first portion and extended from the first portion towards the second surface, and a void enclosed by the STI, wherein the void is at least partially disposed within the second portion of the STI.

公开(公告)号：US20240088187A1

公开(公告)日：2024-03-14

申请号：US18149240

申请日：2023-01-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih Cheng Shih ,  Tsun-Kai Tsao ,  Jiech-Fun Lu ,  Hung-Wen Hsu ,  Bing Cheng You ,  Wen-Chang Kuo

IPC分类号： H01L27/146

CPC分类号： H01L27/1463 ,  H01L27/14643 ,  H01L27/14689

摘要： Trenches in which to form a back side isolation structure for an array of CMOS image sensors are formed by a cyclic process that allows the trenches to be kept narrow. Each cycle of the process includes etching to add a depth segment to the trenches and coating the depth segment with an etch-resistant coating. The following etch step will break through the etch-resistant coating at the bottom of the trench but the etch-resistant coating will remain in the upper part of the trench to limit lateral etching and substrate damage. The resulting trenches have a series of vertically spaced nodes. The process may result in a 10% increase in photodiode area and a 30-40% increase in full well capacity.

公开(公告)号：US11855159B2

公开(公告)日：2023-12-26

申请号：US17680194

申请日：2022-02-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Ta Wu ,  Chia-Shiung Tsai ,  Jiech-Fun Lu ,  Kuo-Hwa Tzeng ,  Shih-Pei Chou ,  Yu-Hung Cheng ,  Yeur-Luen Tu

IPC分类号： H01L29/40 ,  H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L21/324 ,  H01L21/66 ,  H01L21/311

CPC分类号： H01L29/408 ,  H01L21/02238 ,  H01L21/31111 ,  H01L21/3247 ,  H01L21/76254 ,  H01L22/26 ,  H01L29/0649

摘要： Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate without implantation radiation and/or plasma damage. In some embodiments, a device layer is epitaxially formed on a sacrificial substrate and an insulator layer is formed on the device layer. The insulator layer may, for example, be formed with a net charge that is negative or neutral. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates. The sacrificial substrate is removed, and the device layer is cyclically thinned until the device layer has a target thickness. Each thinning cycle comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing.

公开(公告)号：US20230387148A1

公开(公告)日：2023-11-30

申请号：US18360214

申请日：2023-07-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming Chyi Liu ,  Jiech-Fun Lu

IPC分类号： H01L27/146 ,  H01L31/0232

CPC分类号： H01L27/14605 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14685 ,  H01L31/0232

摘要： Various embodiments of the present disclosure are directed towards an image sensor. The image sensor comprises a plurality of photodetectors disposed within a substrate. A metal grid layer is disposed over the substrate. The metal grid layer comprises a metal grid structure overlying a central pixel region of the substrate. The metal grid layer continuously extends from the central pixel region to a peripheral pixel region of the substrate that laterally encloses the central pixel region. An upper metal structure is disposed over the metal grid layer. The upper metal structure overlies the peripheral pixel region. The upper metal structure is laterally offset from the metal grid structure. A lower surface of the upper metal structure is disposed vertically over an upper surface of the metal grid structure.