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    Semiconductor device having a thermal contact and method of making
    1.
    发明授权
    Semiconductor device having a thermal contact and method of making 有权

    公开(公告)号：US12142542B2

    公开(公告)日：2024-11-12

    申请号：US18447927

    申请日：2023-08-10

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC CHINA COMPANY, LIMITED

    Inventor： Jian Wu ,  Feng Han ,  Shuai Zhang

    IPC: H01L23/00 ,  H01L21/48 ,  H01L23/36 ,  H01L23/367 ,  H01L27/12

    Abstract: An integrated circuit includes a substrate and a semiconductor material layer over the substrate. The integrated circuit includes a first source structure in the semiconductor material layer. The first source structure includes a first doped well. The integrated circuit includes a drain structure in the semiconductor material layer. The drain structure includes a second doped well. The integrated circuit includes a second source structure in the semiconductor material layer. The second source structure includes a third doped well. The drain structure is between the first source structure and the second source structure. The integrated circuit includes a first deep trench isolation (DTI) extending through the first doped well; and a first thermal contact extending through the first DTI. The thermal contact is in direct contact with the substrate. The first DTI is between the thermal contact and the first doped well.

    Semiconductor device having buried bias pads
    2.
    发明授权
    Semiconductor device having buried bias pads 有权

    公开(公告)号：US11355518B2

    公开(公告)日：2022-06-07

    申请号：US16936030

    申请日：2020-07-22

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. ,  TSMC CHINA COMPANY, LIMITED

    Inventor： Jian Wu ,  Feng Han ,  Shuai Zhang

    IPC: H01L27/12 ,  H01L21/74 ,  H01L21/84 ,  H01L23/535

    Abstract: An integrated circuit includes a bias pad within a buried oxide layer. A layer of semiconductor material is over the buried oxide layer. The layer of semiconductor material includes a doped regions for a transistor. An inter layer dielectric (ILD) material covers the layer of semiconductor material and a gate electrode for the transistor. The integrated circuit includes one or more bias contacts extending through the ILD material within an isolation region in the layer of semiconductor material. Bias contacts electrically connect to the first bias pad. The isolation structure insulates the one or more bias contacts from the doped regions of the transistor within the layer of semiconductor material. The one or more bias contacts are electrically connected to an interconnection structure of the integrated circuit which is configured to connect a voltage source to the bias pad.

    Thermal substrate contact
    6.
    发明授权
    Thermal substrate contact 有权

    公开(公告)号：US11862527B2

    公开(公告)日：2024-01-02

    申请号：US17122749

    申请日：2020-12-15

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC CHINA COMPANY, LIMITED

    Inventor： Jian Wu ,  Feng Han ,  Shuai Zhang

    IPC: H01L23/00 ,  H01L23/36 ,  H01L21/48 ,  H01L27/12

    CPC classification number: H01L23/36 ,  H01L21/4871 ,  H01L21/4875 ,  H01L27/1203

    Abstract: An integrated circuit includes an oxide layer over a substrate; a layer of semiconductor material over the oxide layer and which includes a P-well, an N-well, and a channel of a transistor; and a thermal substrate contact extending through the layer of semiconductor material and the oxide layer, and against a top surface of the substrate. A thermal substrate contact increases the ability to remove heat produced from the integrated circuit transistors out of the integrated circuit. A thermal substrate contact which traverses the oxide layer over a substrate provides a secondary path for heat out of an integrated circuit (or, alternatively, out of a substrate through the integrated circuit) to cool the integrated circuit.

    Method of making semiconductor device having buried bias pad
    10.
    发明授权
    Method of making semiconductor device having buried bias pad 有权

    公开(公告)号：US11973083B2

    公开(公告)日：2024-04-30

    申请号：US17741410

    申请日：2022-05-10

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC CHINA COMPANY, LIMITED

    Inventor： Jian Wu ,  Feng Han ,  Shuai Zhang

    IPC: H01L27/12 ,  H01L21/74 ,  H01L21/84 ,  H01L23/535

    CPC classification number: H01L27/1203 ,  H01L21/743 ,  H01L21/84 ,  H01L23/535 ,  H01L27/1207

    Abstract: A method of making an integrated circuit includes surrounding a first bias pad with dielectric material of a buried oxide layer. The method includes adding dopants to a layer of semiconductor material over the first bias pad. The method includes depositing a gate dielectric and a gate electrode over a top surface of the layer of semiconductor material. The method includes etching the gate dielectric and the gate electrode to isolate a gate electrode over the layer of semiconductor material. The method includes depositing an inter layer dielectric (ILD) material over the gate electrode and the layer of semiconductor material. The method includes etching at least one bias contact opening down to the first bias pad. The method includes filling the at least one bias contact opening with a bias contact material. The method includes electrically connecting at least one bias contact to an interconnect structure of the semiconductor device.

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