公开(公告)号：US12100767B2

公开(公告)日：2024-09-24

申请号：US17669317

申请日：2022-02-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Cheng-Ta Wu ,  Chii-Ming Wu ,  Shiu-Ko Jangjian ,  Kun-Tzu Lin ,  Lan-Fang Chang

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/49

CPC分类号： H01L29/7856 ,  H01L21/02321 ,  H01L21/02323 ,  H01L21/28114 ,  H01L21/28158 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/823456 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/512 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7851 ,  H01L29/495 ,  H01L29/513

摘要： A semiconductor includes a gate stack over a substrate. The semiconductor device further includes an interlayer dielectric (ILD) at least partially enclosing the gate stack. The ILD includes a portion doped with a large species material, wherein the portion includes a first sidewall substantially perpendicular to a top-most surface of the ILD, and the portion includes a second sidewall having a positive angle with respect to the first sidewall.

公开(公告)号：US12062539B2

公开(公告)日：2024-08-13

申请号：US18328102

申请日：2023-06-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Ta Wu ,  Chia-Ta Hsieh ,  Kuo Wei Wu ,  Yu-Chun Chang ,  Ying Ling Tseng

IPC分类号： H01L21/02 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06

CPC分类号： H01L21/02359 ,  H01L21/76251 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649

摘要： Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a handle substrate; a device layer overlying the handle substrate; and an insulator layer separating the handle substrate from the device layer. The insulator layer meets the device layer at a first interface and meets the handle substrate at a second interface. The insulator layer comprises a getter material having a getter concentration profile. The handle substrate contains getter material and has a handle getter concentration profile. The handle getter concentration profile has a peak at the second interface and a gradual decline beneath the second interface until reaching a handle getter concentration.

公开(公告)号：US11929379B2

公开(公告)日：2024-03-12

申请号：US17842138

申请日：2022-06-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Min-Ying Tsai ,  Cheng-Ta Wu ,  Yeur-Luen Tu

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L27/146

CPC分类号： H01L27/14634 ,  H01L21/7684 ,  H01L23/481 ,  H01L27/14636 ,  H01L27/1469

摘要： Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, the method includes forming a through substrate via (TSV) in a first substrate. The TSV continuously extends from a first surface of the first substrate to a second surface of the first substrate. A conductive contact is formed on the second surface of the first substrate. The conductive contact comprises a first conductive layer disposed on the TSV. An upper conductive layer is formed between the conductive contact and the TSV. The upper conductive layer comprises a silicide of a conductive material of the first conductive layer.

公开(公告)号：US11830764B2

公开(公告)日：2023-11-28

申请号：US17869837

申请日：2022-07-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Ta Wu ,  Chia-Shiung Tsai ,  Jiech-Fun Lu ,  Kuan-Liang Liu ,  Shih-Pei Chou ,  Yu-Hung Cheng ,  Yeur-Luen Tu

IPC分类号： H01L21/00 ,  H01L21/762 ,  H01L21/3213 ,  H01L21/306

CPC分类号： H01L21/76264 ,  H01L21/30604 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/76256

摘要： Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.

公开(公告)号：US11611005B2

公开(公告)日：2023-03-21

申请号：US16993824

申请日：2020-08-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Hung Cheng ,  Chia-Shiung Tsai ,  Cheng-Ta Wu ,  Xiaomeng Chen ,  Yen-Chang Chu ,  Yeur-Luen Tu

IPC分类号： H01L31/103 ,  H01L31/0352 ,  H01L31/0232 ,  H01L31/18 ,  H01L31/028 ,  H01L31/109 ,  H01L27/146 ,  H01L31/105

摘要： A photo-sensitive device includes a uniform layer, a gradated buffer layer over the uniform layer, a silicon layer over the gradated buffer layer, a photo-sensitive light-sensing region in the uniform layer and the silicon layer, a device layer on the silicon layer, and a carrier wafer bonded to the device layer.

公开(公告)号：US20220310691A1

公开(公告)日：2022-09-29

申请号：US17842138

申请日：2022-06-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Min-Ying Tsai ,  Cheng-Ta Wu ,  Yeur-Luen Tu

IPC分类号： H01L27/146 ,  H01L21/768 ,  H01L23/48

摘要： Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, the method includes forming a through substrate via (TSV) in a first substrate. The TSV continuously extends from a first surface of the first substrate to a second surface of the first substrate. A conductive contact is formed on the second surface of the first substrate. The conductive contact comprises a first conductive layer disposed on the TSV. An upper conductive layer is formed between the conductive contact and the TSV. The upper conductive layer comprises a silicide of a conductive material of the first conductive layer.

公开(公告)号：US20220238662A1

公开(公告)日：2022-07-28

申请号：US17680194

申请日：2022-02-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Ta Wu ,  Chia-Shiung Tsai ,  Jiech-Fun Lu ,  Kuo-Hwa Tzeng ,  Shih-Pei Chou ,  Yu-Hung Cheng ,  Yeur-Luen Tu

IPC分类号： H01L29/40 ,  H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L21/324 ,  H01L21/66 ,  H01L21/311

摘要： Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate without implantation radiation and/or plasma damage. In some embodiments, a device layer is epitaxially formed on a sacrificial substrate and an insulator layer is formed on the device layer. The insulator layer may, for example, be formed with a net charge that is negative or neutral. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates. The sacrificial substrate is removed, and the device layer is cyclically thinned until the device layer has a target thickness. Each thinning cycle comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing.

公开(公告)号：US20220059364A1

公开(公告)日：2022-02-24

申请号：US17519765

申请日：2021-11-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Chen-Hao Chiang ,  Alexander Kalnitsky ,  Yeur-Luen Tu ,  Eugene Chen

IPC分类号： H01L21/322 ,  H01L23/66 ,  H01L21/762 ,  H01L29/34 ,  H01L29/06

摘要： In some embodiments, the present disclosure relates to a high-resistivity silicon-on-insulator (SOI) substrate, including a first polysilicon layer arranged over a semiconductor substrate. A second polysilicon layer is arranged over the first polysilicon layer, and a third polysilicon layer is arranged over the second polysilicon layer. An active semiconductor layer over an insulator layer may be arranged over the third polysilicon layer. The second polysilicon layer has an elevated concentration of oxygen compared to the first and third polysilicon layers.

公开(公告)号：US11171039B2

公开(公告)日：2021-11-09

申请号：US15939883

申请日：2018-03-29

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Min-Ying Tsai ,  Cheng-Ta Wu ,  Yu-Hung Cheng ,  Yeur-Luen Tu

IPC分类号： H01L21/763 ,  H01L29/04 ,  H01L29/32 ,  H01L21/02 ,  H01L21/762 ,  H01L29/10 ,  H01L23/66

摘要： A composite semiconductor substrate includes a semiconductor substrate, an oxygen-doped crystalline semiconductor layer and an insulative layer. The oxygen-doped crystalline semiconductor layer is over the semiconductor substrate, and the oxygen-doped crystalline semiconductor layer includes a crystalline semiconductor material and a plurality of oxygen dopants. The insulative layer is over the oxygen-doped crystalline semiconductor layer.

公开(公告)号：US11024716B2

公开(公告)日：2021-06-01

申请号：US16709260

申请日：2019-12-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Cheng-Ta Wu ,  Yi-Hsien Lee ,  Wei-Ming You ,  Ting-Chun Wang

IPC分类号： H01L29/167 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L21/02

摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate; a fin structure, disposed over the substrate; a gate structure, disposed over the substrate and covering a portion of the fin structure; a first sidewall, disposed over the substrate and surrounding a lower portion of the gate structure; and a second sidewall, disposed over the first sidewall and directly surrounding an upper portion of the gate structure, wherein the first sidewall is orthogonal to the second sidewall.