公开(公告)号：US20230282476A1

公开(公告)日：2023-09-07

申请号：US17683567

申请日：2022-03-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Lung Yuan Pan ,  Chen-Hao Chiang ,  Chih-Ming Chen

IPC分类号： H01L21/02 ,  H01L21/762 ,  H01L31/0352 ,  H01L31/105 ,  H01L31/18

CPC分类号： H01L21/02532 ,  H01L21/76251 ,  H01L21/0262 ,  H01L31/035281 ,  H01L31/105 ,  H01L31/1808

摘要： In some embodiments, the present disclosure relates to a semiconductor device, including a substrate including a first semiconductor material and a semiconductor layer extending into an upper surface of the substrate and including a second semiconductor material with a different band gap than the first semiconductor material. The semiconductor device also includes a passive cap including a first dielectric material and disposed along the upper surface of the substrate and on opposite sides of the semiconductor layer, and a photodetector in the semiconductor layer. The first dielectric material includes silicon nitride.

公开(公告)号：US20220059364A1

公开(公告)日：2022-02-24

申请号：US17519765

申请日：2021-11-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Chen-Hao Chiang ,  Alexander Kalnitsky ,  Yeur-Luen Tu ,  Eugene Chen

IPC分类号： H01L21/322 ,  H01L23/66 ,  H01L21/762 ,  H01L29/34 ,  H01L29/06

摘要： In some embodiments, the present disclosure relates to a high-resistivity silicon-on-insulator (SOI) substrate, including a first polysilicon layer arranged over a semiconductor substrate. A second polysilicon layer is arranged over the first polysilicon layer, and a third polysilicon layer is arranged over the second polysilicon layer. An active semiconductor layer over an insulator layer may be arranged over the third polysilicon layer. The second polysilicon layer has an elevated concentration of oxygen compared to the first and third polysilicon layers.

公开(公告)号：US10937900B2

公开(公告)日：2021-03-02

申请号：US15136309

申请日：2016-04-22

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Po-Chun Liu ,  Chi-Ming Chen ,  Yao-Chung Chang ,  Jiun-Lei Jerry Yu ,  Chen-Hao Chiang ,  Chung-Yi Yu

IPC分类号： H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H01L29/49

摘要： The present disclosure provides a semiconductor structure, including a substrate, a first III-V layer over the substrate, having a first band gap, and a second III-V layer over the first III-V layer, having a second band gap. The second III-V layer includes a first surface in contact with the first III-V layer and a second surface opposite to the first surface. The second band gap at the second surface is greater than the second band gap at the first surface. The present disclosure also provides a manufacturing method of the aforesaid semiconductor structure.

公开(公告)号：US09548376B2

公开(公告)日：2017-01-17

申请号：US14976943

申请日：2015-12-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Po-Chun Liu ,  Chi-Ming Chen ,  Chen-Hao Chiang ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/778 ,  H01L21/02 ,  H01L29/20 ,  H01L29/267 ,  H01L29/207

CPC分类号： H01L29/66431 ,  H01L21/02378 ,  H01L21/02389 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/267 ,  H01L29/66462 ,  H01L29/7783

摘要： A method of manufacturing a semiconductor device includes forming a barrier structure over a substrate. The method further includes forming a channel layer over the barrier structure. The method further includes depositing an active layer over the channel layer. The method further includes forming source/drain electrodes over the channel layer. The method further includes annealing the source/drain electrodes to form ohmic contacts in the active layer under the source/drain electrodes.

摘要翻译： 制造半导体器件的方法包括在衬底上形成阻挡结构。 该方法还包括在阻挡结构上形成沟道层。 该方法还包括在沟道层上沉积有源层。 该方法还包括在沟道层上形成源极/漏极。 该方法还包括对源/漏电极进行退火以在源极/漏极下方的有源层中形成欧姆接触。

公开(公告)号：US11551927B2

公开(公告)日：2023-01-10

申请号：US17089147

申请日：2020-11-04

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Po-Chun Liu ,  Chung-Chieh Hsu ,  Chi-Ming Chen ,  Chung-Yi Yu ,  Chen-Hao Chiang ,  Min-Chang Ching

IPC分类号： H01L29/778 ,  H01L21/02 ,  H01L29/66 ,  H01L29/45 ,  H01L29/20 ,  H01L29/205 ,  H01L29/201 ,  H01L29/10 ,  H01L29/207

摘要： A high electron mobility transistor includes: a first semiconductor layer over a substrate, and a second semiconductor layer over the first semiconductor layer, the second semiconductor layer having a band gap discontinuity with the first semiconductor layer, and at the first semiconductor layer and/or the second conductive layer includes indium. A top layer is over the second semiconductor layer, and a metal layer is over, and extends into, the top layer, the top layer separating the metal layer from the second semiconductor layer. A gate electrode is over the top layer, a third semiconductor layer being between the gate electrode and the top layer, where a sidewall of the third semiconductor layer and a sidewall of the metal layer are separated. A source and drain are on opposite sides of the gate electrode, the top layer extending continuously from below the source, below the gate electrode, and below the drain.

公开(公告)号：US09899493B2

公开(公告)日：2018-02-20

申请号：US15377622

申请日：2016-12-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hao Chiang ,  Po-Chun Liu ,  Han-Chin Chiu ,  Chi-Ming Chen ,  Chung-Yi Yu

IPC分类号： H01L29/66 ,  H01L21/265 ,  H01L21/311 ,  H01L21/02 ,  H01L21/324 ,  H01L21/283

CPC分类号： H01L29/66462 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/2654 ,  H01L21/283 ,  H01L21/31111 ,  H01L21/324 ,  H01L29/122 ,  H01L29/2003 ,  H01L29/66522 ,  H01L29/7783

摘要： A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is smaller than the first band gap. The HEMT further includes a third III-V compound layer having a third band gap over the second III-V compound layer, wherein the third band gap is greater than the first band gap. A gate electrode is formed over the third III-V compound layer. A source region and a drain region are over the third III-V compound layer and on opposite sides of the gate electrode.

公开(公告)号：US09245991B2

公开(公告)日：2016-01-26

申请号：US13964530

申请日：2013-08-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Po-Chun Liu ,  Chi-Ming Chen ,  Chen-Hao Chiang ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC分类号： H01L21/44 ,  H01L29/778 ,  H01L29/66 ,  H01L29/20

CPC分类号： H01L29/66431 ,  H01L21/02378 ,  H01L21/02389 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/267 ,  H01L29/66462 ,  H01L29/7783

摘要： A semiconductor device includes a substrate, a channel layer over the substrate, an active layer over the channel layer, and a barrier structure between the substrate and the channel layer. The active layer is configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer. The barrier structure is configured to block diffusion of at least one of a material of the substrate or a dopant toward the channel layer.

摘要翻译： 半导体器件包括衬底，衬底上的沟道层，沟道层上的有源层以及衬底和沟道层之间的阻挡结构。 有源层被配置成沿沟道层和有源层之间的界面在沟道层中形成二维电子气（2DEG）。 阻挡结构被配置为阻挡衬底或掺杂剂的材料中的至少一种朝向沟道层的扩散。

公开(公告)号：US09076854B2

公开(公告)日：2015-07-07

申请号：US14010309

申请日：2013-08-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Po-Chun Liu ,  Chi-Ming Chen ,  Chen-Hao Chiang ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC分类号： H01L31/072 ,  H01L29/778 ,  H01L29/205 ,  H01L29/20 ,  H01L29/66

CPC分类号： H01L29/66462 ,  H01L21/0254 ,  H01L29/0657 ,  H01L29/1033 ,  H01L29/1066 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66431 ,  H01L29/7786

摘要： A semiconductor device includes a substrate, a channel layer over the substrate, an active layer over the channel layer, a gate structure over the active layer, and a barrier layer between the gate structure and the active layer. The active layer is configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer. The gate structure is configured to deplete the 2DEG under the gate structure. The gate structure includes a dopant. The barrier layer is configured to block diffusion of the dopant from the gate structure into the active layer.

摘要翻译： 半导体器件包括衬底，衬底上的沟道层，沟道层上的有源层，有源层上的栅极结构以及栅极结构和有源层之间的势垒层。 有源层被配置成沿沟道层和有源层之间的界面在沟道层中形成二维电子气（2DEG）。 栅极结构被配置为在栅极结构下耗尽2DEG。 栅极结构包括掺杂剂。 阻挡层被配置为阻止掺杂剂从栅极结构扩散到有源层中。

公开(公告)号：US08975641B1

公开(公告)日：2015-03-10

申请号：US14010268

申请日：2013-08-26

申请人： Taiwan Semiconductor Manufacturing Company Ltd.

发明人： Chen-Hao Chiang ,  Po-Chun Liu ,  Chi-Ming Chen ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC分类号： H01L31/0256 ,  H01L29/778 ,  H01L29/205 ,  H01L29/20 ,  H01L29/66

CPC分类号： H01L29/7786 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/66462

摘要： A transistor includes a substrate, a channel layer over the substrate and an active layer over the channel layer. The active layer includes a gradient having a first concentration of a first material at an interface with the channel layer and a second concentration of the first material at a surface opposite the channel layer, and the first concentration is higher than the second concentration.

摘要翻译： 晶体管包括衬底，衬底上的沟道层和沟道层上的有源层。 活性层包括在与沟道层界面处具有第一材料的第一浓度的梯度和在与沟道层相对的表面处的第一材料的第二浓度，并且第一浓度高于第二浓度。

公开(公告)号：US12074036B2

公开(公告)日：2024-08-27

申请号：US17519765

申请日：2021-11-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Chen-Hao Chiang ,  Alexander Kalnitsky ,  Yeur-Luen Tu ,  Eugene Chen

IPC分类号： H01L21/322 ,  H01L21/762 ,  H01L23/66 ,  H01L29/06 ,  H01L29/34

CPC分类号： H01L21/3226 ,  H01L21/7624 ,  H01L23/66 ,  H01L29/0649 ,  H01L29/34

摘要： In some embodiments, the present disclosure relates to a high-resistivity silicon-on-insulator (SOI) substrate, including a first polysilicon layer arranged over a semiconductor substrate. A second polysilicon layer is arranged over the first polysilicon layer, and a third polysilicon layer is arranged over the second polysilicon layer. An active semiconductor layer over an insulator layer may be arranged over the third polysilicon layer. The second polysilicon layer has an elevated concentration of oxygen compared to the first and third polysilicon layers.