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    CMOS structure including non-planar hybrid orientation substrate with planar gate electrodes and method for fabrication
    31.
    发明授权
    CMOS structure including non-planar hybrid orientation substrate with planar gate electrodes and method for fabrication 有权
    CMOS结构包括具有平面栅电极的非平面混合取向衬底和制造方法

    公开(公告)号：US08569159B2

    公开(公告)日：2013-10-29

    申请号：US13453215

    申请日：2012-04-23

    Applicant: Kangguo Cheng

    Inventor： Kangguo Cheng

    IPC: H01L21/3205

    CPC classification number: H01L21/823807 ,  H01L21/2807 ,  H01L21/28079 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/51 ,  H01L29/665

    Abstract: A semiconductor structure and a method for fabricating the semiconductor structure include a hybrid orientation substrate having a first active region having a first crystallographic orientation that is vertically separated from a second active region having a second crystallographic orientation different than the first crystallographic orientation. A first field effect device having a first gate electrode is located and formed within and upon the first active region and a second field effect device having a second gate electrode is located and formed within and upon the second active region. Upper surfaces of the first gate electrode and the second gate electrode are coplanar. The structure and method allow for avoidance of epitaxial defects generally encountered when using hybrid orientation technology substrates that include coplanar active regions.

    Abstract translation: 半导体结构和半导体结构的制造方法包括混合取向基片，其具有第一有源区，其具有与具有不同于第一晶体取向的第二结晶取向的第二有源区垂直分离的第一晶体取向。 具有第一栅电极的第一场效应器件被定位并形成在第一有源区内和第一有源区上，并且具有第二栅电极的第二场效应器件被定位并形成在第二有源区内和之上。 第一栅电极和第二栅电极的上表面是共面的。 该结构和方法允许避免当使用包括共面活性区域的混合取向技术衬底时通常遇到的外延缺陷。

    Field effect transistors with low body resistance and self-balanced body potential
    32.
    发明授权
    Field effect transistors with low body resistance and self-balanced body potential 有权
    具有低体电阻和自平衡体电位的场效应晶体管

    公开(公告)号：US08564069B1

    公开(公告)日：2013-10-22

    申请号：US13590212

    申请日：2012-08-21

    Applicant: Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

    Inventor： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

    IPC: H01L27/088

    CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/823437 ,  H01L27/027 ,  H01L29/0615 ,  H01L29/78

    Abstract: Embodiments of the invention relate generally to semiconductor devices and, more particularly, to semiconductor devices having field effect transistors (FETs) with a low body resistance and, in some embodiments, a self-balanced body potential where multiple transistors share same body potential. In one embodiment, the invention includes a field effect transistor (FET) comprising a source within a substrate, a drain within the substrate, and an active gate atop the substrate and between the source and the drain, an inactive gate structure atop the substrate and adjacent the source or the drain, a body adjacent the inactive gate, and a discharge path within the substrate for releasing a charge from the FET, the discharge path lying between the active gate of the FET and the body, wherein the discharge path is substantially perpendicular to a width of the active gate.

    Abstract translation: 本发明的实施例大体上涉及半导体器件，更具体地，涉及具有低体电阻的场效应晶体管（FET）的半导体器件，在一些实施例中，具有多个晶体管共享相同体电位的自平衡体电位。 在一个实施例中，本发明包括场效应晶体管（FET），其包括在衬底内的源极，衬底内的漏极，以及位于衬底顶部和源极与漏极之间的有源栅极，在衬底顶部的非活性栅极结构， 邻近源极或漏极，与非活性栅极相邻的主体以及衬底内的用于从FET释放电荷的放电路径，放电路径位于FET的有源栅极和主体之间，其中放电路径基本上 垂直于有源栅极的宽度。

    SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES, AND METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES
    33.
    发明申请
    SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES, AND METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES 有权
    具有精细结构的半导体器件，以及形成具有结构的半导体器件的方法

    公开(公告)号：US20130270655A1

    公开(公告)日：2013-10-17

    申请号：US13448749

    申请日：2012-04-17

    Applicant: Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

    Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

    IPC: H01L29/78 ,  H01L21/336 ,  H01L21/20

    CPC classification number: H01L29/78 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/20 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    Abstract: A semiconductor device including at least two fin structures on a substrate surface and a functional gate structure present on the at least two fin structures. The functional gate structure includes at least one gate dielectric that is in direct contact with at least the sidewalls of the two fin structures, and at least one gate conductor on the at least one gate dielectric. The sidewall of the gate structure is substantially perpendicular to the upper surface of the substrate surface, wherein the plane defined by the sidewall of the gate structure and a plane defined by an upper surface of the substrate surface intersect at an angle of 90°+/−5°. An epitaxial semiconductor material is in direct contact with the at least two fin structures.

    Abstract translation: 一种半导体器件，包括在衬底表面上的至少两个鳍结构和存在于所述至少两个鳍结构上的功能栅结构。 功能栅极结构包括至少一个与至少两个鳍结构的侧壁直接接触的栅极电介质，以及至少一个栅极电介质上的至少一个栅极导体。 栅极结构的侧壁基本上垂直于衬底表面的上表面，其中由栅极结构的侧壁限定的平面和由衬底表面的上表面限定的平面以90°±/ -5°。 外延半导体材料与至少两个翅片结构直接接触。

    STRAINED SOI FINFET ON EPITAXIALLY GROWN BOX
    34.
    发明申请
    STRAINED SOI FINFET ON EPITAXIALLY GROWN BOX 审中-公开
    外延生长框架上的应变SOI结构

    公开(公告)号：US20130270638A1

    公开(公告)日：2013-10-17

    申请号：US13445959

    申请日：2012-04-13

    Applicant: Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan

    Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/785 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848

    Abstract: A semiconductor structure includes an epitaxial insulator layer located on a substrate. A fin structure is located on the epitaxial insulator layer, where at least one epitaxial source-drain region having an embedded stressor is located on the epitaxial insulator layer and abuts at least one sidewall associated with the fin structure. The epitaxial source-drain region having the embedded stressor provides stress along the fin structure such that the provided stress is based on a lattice mismatch between the epitaxial source-drain region, and both the epitaxial insulator layer and the one side-wall associated with the fin structure.

    Abstract translation: 半导体结构包括位于衬底上的外延绝缘体层。 翅片结构位于外延绝缘体层上，其中具有嵌入的应力源的至少一个外延源极 - 漏极区域位于外延绝缘体层上并邻接与翅片结构相关联的至少一个侧壁。 具有嵌入的应力源的外延源极 - 漏极区域沿着鳍状结构提供应力，使得所提供的应力基于外延源极 - 漏极区域和外延绝缘体层与与该外部源极 - 漏极区域相关联的一个侧壁之间的晶格失配 翅片结构。

    Strained thin body CMOS device having vertically raised source/drain stressors with single spacer
    37.
    发明授权
    Strained thin body CMOS device having vertically raised source/drain stressors with single spacer 有权
    应变的薄体CMOS器件具有单个间隔物的垂直升高的源/漏应力源

    公开(公告)号：US08546228B2

    公开(公告)日：2013-10-01

    申请号：US12816399

    申请日：2010-06-16

    Applicant: Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    Inventor： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    IPC: H01L21/336

    CPC classification number: H01L29/66477 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78618

    Abstract: A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure.

    Abstract translation: 一种形成晶体管器件的方法包括在半导体衬底上形成图案化栅极结构; 在半导体衬底上形成间隔层和图案化栅极结构; 去除间隔层的水平设置部分，以形成邻近图案化栅极结构的垂直侧壁间隔物; 以及在所述半导体衬底上并且邻近所述垂直侧壁间隔物形成升高的源极/漏极（RSD）结构，其中所述RSD结构具有基本上垂直的侧壁轮廓，以便邻接所述垂直侧壁间隔物并产生压缩和拉伸应变之一 在图案化的栅极结构下方的半导体衬底的沟道区上。

    FinFET with reduced gate to fin overlay sensitivity
    38.
    发明授权
    FinFET with reduced gate to fin overlay sensitivity 有权
    FinFET具有降低的栅极到鳍片覆盖灵敏度

    公开(公告)号：US08518767B2

    公开(公告)日：2013-08-27

    申请号：US11680221

    申请日：2007-02-28

    Applicant: Kangguo Cheng ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  John Edward Sheets, II

    Inventor： Kangguo Cheng ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  John Edward Sheets, II

    IPC: H01L21/336

    CPC classification number: H01L29/785 ,  H01L29/045 ,  H01L29/66818

    Abstract: Embodiments of the invention provide a relatively uniform width fin in a Fin Field Effect Transistors (FinFETs) and apparatus and methods for forming the same. A fin structure may be formed such that the surface of a sidewall portion of the fin structure is normal to a first crystallographic direction. Tapered regions at the end of the fin structure may be normal to a second crystal direction. A crystallographic dependent etch may be performed on the fin structure. The crystallographic dependent etch may remove material from portions of the fin normal to the second crystal direction relatively faster, thereby resulting in a relatively uniform width fin structure.

    Abstract translation: 本发明的实施例提供了Fin场效应晶体管（FinFET）中的相对均匀的宽度鳍片及其形成方法。 翅片结构可以形成为使翅片结构的侧壁部分的表面垂直于第一结晶方向。 翅片结构端部的锥形区域可以垂直于第二晶体方向。 可以对翅片结构进行晶体依赖蚀刻。 晶体依赖蚀刻可以相对较快地从第二晶体方向垂直于翅片的部分去除材料，从而形成相对均匀的宽度鳍片结构。

    On-chip capacitors in combination with CMOS devices on extremely thin semiconductor on insulator (ETSOI) substrates
    40.
    发明授权
    On-chip capacitors in combination with CMOS devices on extremely thin semiconductor on insulator (ETSOI) substrates 有权
    片上电容与CMOS器件结合在非常薄的半导体绝缘体（ETSOI）衬底上

    公开(公告)号：US08507354B2

    公开(公告)日：2013-08-13

    申请号：US13314238

    申请日：2011-12-08

    Applicant: Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznieck

    Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznieck

    IPC: H01L21/20 ,  H01L29/94

    CPC classification number: H01L27/1203 ,  H01L27/0629 ,  H01L29/94

    Abstract: A device including a semiconductor on insulator (SOI) substrate including a semiconductor device region and a capacitor device region. A semiconductor device present in the semiconductor device region. The semiconductor device including a gate structure present on a semiconductor on insulator (SOI) layer of the SOI substrate, extension source and drain regions present in the SOI layer on opposing sides of the gate structure, and raised source and drain regions composed of a first portion of an epitaxial semiconductor material on the SOI layer. A capacitor is present in the capacitor device region, said capacitor including a first electrode comprised of a second portion of the epitaxial semiconductor material that has a same composition and crystal structure as the first portion of the epitaxial semiconductor material, a node dielectric layer present on the second portion of the epitaxial semiconductor material, and a second electrode comprised of a conductive material.

    Abstract translation: 一种包括半导体器件区域和电容器器件区域的绝缘体半导体（SOI）衬底的器件。 存在于半导体器件区域中的半导体器件。 所述半导体器件包括存在于SOI衬底的半导体绝缘体（SOI）层上的栅极结构，存在于栅极结构的相对侧上的SOI层中的延伸源极和漏极区域以及由第一 SOI层上的外延半导体材料的一部分。 在电容器器件区域中存在电容器，所述电容器包括由外延半导体材料的第二部分构成的第一电极，其具有与外延半导体材料的第一部分相同的组成和晶体结构， 外延半导体材料的第二部分和由导电材料组成的第二电极。

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