公开(公告)号：US11842928B2

公开(公告)日：2023-12-12

申请号：US17809944

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Han Tsai ,  Chung-Chiang Wu ,  Cheng-Lung Hung ,  Weng Chang ,  Chi On Chui

IPC: H01L21/8234 ,  H01L21/28 ,  H01L27/088 ,  H01L29/49

CPC classification number: H01L21/82345 ,  H01L21/28088 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/4966

Abstract: A method includes forming a gate dielectric on a semiconductor region, depositing a work-function layer over the gate dielectric, depositing a silicon layer over the work-function layer, and depositing a glue layer over the silicon layer. The work-function layer, the silicon layer, and the glue layer are in-situ deposited. The method further includes depositing a filling-metal over the glue layer; and performing a planarization process, wherein remaining portions of the glue layer, the silicon layer, and the work-function layer form portions of a gate electrode.

公开(公告)号：US20230397442A1

公开(公告)日：2023-12-07

申请号：US18447805

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chenchen Wang ,  Chun-Chieh Lu ,  Chi On Chui ,  Yu-Ming Lin ,  Sai-Hooi Yeong

IPC: H10B63/00 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H10B61/00

CPC classification number: H10B63/84 ,  H01L29/66666 ,  H01L29/78642 ,  H01L29/42392 ,  H10B61/22 ,  H10B63/34

Abstract: A device includes a first transistor over a substrate, a second transistor disposed over the first transistor, and a memory element disposed over the second transistor. The second transistor includes a channel layer, a gate dielectric layer surrounding a sidewall of the channel layer, and a gate electrode surrounding a sidewall of the gate dielectric layer.

公开(公告)号：US20230395702A1

公开(公告)日：2023-12-07

申请号：US18364352

申请日：2023-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ju Chen ,  Chung-Ting Ko ,  Ya-Lan Chang ,  Ting-Gang Chen ,  Tai-Chun Huang ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78 ,  H01L21/02 ,  H01L21/033

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L29/0669 ,  H01L29/785 ,  H01L21/02178 ,  H01L21/0332 ,  H01L29/66636

Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.

公开(公告)号：US11837660B2

公开(公告)日：2023-12-05

申请号：US17674361

申请日：2022-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3115 ,  H01L29/786

CPC classification number: H01L29/78391 ,  H01L21/02603 ,  H01L21/28185 ,  H01L21/3115 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78696

Abstract: A semiconductor device and method of manufacture are provided which utilizes metallic seeds to help crystallize a ferroelectric layer. In an embodiment a metal layer and a ferroelectric layer are formed adjacent to each other and then the metal layer is diffused into the ferroelectric layer. Once in place, a crystallization process is performed which utilizes the material of the metal layer as seed crystals.

公开(公告)号：US20230387012A1

公开(公告)日：2023-11-30

申请号：US17819679

申请日：2022-08-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hsien Cheng ,  Zhen-Cheng Wu ,  Tze-Liang Lee ,  Chi On Chui

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L21/768

CPC classification number: H01L23/5286 ,  H01L23/5226 ,  H01L23/53238 ,  H01L29/42392 ,  H01L29/0669 ,  H01L29/78696 ,  H01L21/76877 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/76805 ,  H01L21/76843

Abstract: Methods of forming vias for coupling source/drain regions to backside interconnect structures in semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a conductive feature adjacent a gate structure; a dielectric layer on the conductive feature and the gate structure; a metal via embedded in the dielectric layer; and a liner layer between and in contact with the metal via and the dielectric layer, the liner layer being boron nitride.

公开(公告)号：US11824100B2

公开(公告)日：2023-11-21

申请号：US17232282

申请日：2021-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L29/16 ,  H01L29/20 ,  H01L29/49 ,  H01L21/285 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/4966 ,  H01L21/28556 ,  H01L29/401 ,  H01L29/66545

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate stack over an active region of a substrate. The gate stack includes a gate dielectric layer and a first work function layer over the gate dielectric layer. The first work function layer includes a plurality of first layers and a plurality of second layers arranged in an alternating manner over the gate dielectric layer. The plurality of first layers include a first material. The plurality of second layers include a second material different from the first material.

公开(公告)号：US20230369471A1

公开(公告)日：2023-11-16

申请号：US18358066

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Chih-Yu Chang ,  Sai-Hooi Yeong ,  Chi On Chui ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L29/6684 ,  H01L29/7851 ,  H01L29/66545 ,  H01L29/513 ,  H01L29/66795 ,  H01L29/516

Abstract: Circuit devices and methods of forming the same are provided. In one embodiment, a method includes receiving a workpiece that includes a substrate and a fin extending from the substrate, forming a first ferroelectric layer on the fin, forming a dummy gate structure over a channel region of the fin, forming a gate spacer over sidewalls of the dummy gate structure, forming an inter-level dielectric layer over the workpiece, removing the dummy gate structure to expose the first ferroelectric layer over the channel region of the fin, and forming a gate electrode over the exposed first ferroelectric layer over the channel region of the fin.

公开(公告)号：US20230360918A1

公开(公告)日：2023-11-09

申请号：US18356860

申请日：2023-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Yang Lai ,  Chun-Yen Peng ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L21/28 ,  H01L21/3115 ,  H01L29/51 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L21/28185 ,  H01L21/3115 ,  H01L29/513 ,  H01L27/0886 ,  H01L21/823462 ,  H01L21/823431

Abstract: A method includes forming an oxide layer on a semiconductor region, and depositing a first high-k dielectric layer over the oxide layer. The first high-k dielectric layer is formed of a first high-k dielectric material. The method further includes depositing a second high-k dielectric layer over the first high-k dielectric layer, wherein the second high-k dielectric layer is formed of a second high-k dielectric material different from the first high-k dielectric material, depositing a dipole film over and contacting a layer selected from the first high-k dielectric layer and the second high-k dielectric layer, performing an annealing process to drive-in a dipole dopant in the dipole film into the layer, removing the dipole film, and forming a gate electrode over the second high-k dielectric layer.

公开(公告)号：US11810961B2

公开(公告)日：2023-11-07

申请号：US17220076

申请日：2021-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/4908 ,  H01L21/02603 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78696

Abstract: In an embodiment, a device includes: a p-type transistor including: a first channel region; a first gate dielectric layer on the first channel region; a tungsten-containing work function tuning layer on the first gate dielectric layer; and a first fill layer on the tungsten-containing work function tuning layer; and an n-type transistor including: a second channel region; a second gate dielectric layer on the second channel region; a tungsten-free work function tuning layer on the second gate dielectric layer; and a second fill layer on the tungsten-free work function tuning layer.

公开(公告)号：US20230343822A1

公开(公告)日：2023-10-26

申请号：US17867804

申请日：2022-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Ji-Cheng Chen ,  Weng Chang ,  Chi On Chui

IPC: H01L29/06 ,  H01L29/775 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/775 ,  H01L29/66439 ,  H01L29/78696

Abstract: In an embodiment, a device includes: a first nanostructure; a gate dielectric layer around the first nanostructure; a first p-type work function tuning layer on the gate dielectric layer; a dielectric barrier layer on the first p-type work function tuning layer; and a second p-type work function tuning layer on the dielectric barrier layer, the dielectric barrier layer being thinner than the first p-type work function tuning layer and the second p-type work function tuning layer.