公开(公告)号：US11935754B2

公开(公告)日：2024-03-19

申请号：US17854175

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L21/28568 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/78696

Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a high-k gate dielectric around the first nanostructure and the second nanostructure, the high-k gate dielectric having a first portion on a top surface of the first nano structure and a second portion on a bottom surface of the second nanostructure; and a gate electrode over the high-k gate dielectric. The gate electrode comprises: a first work function metal around the first nanostructure and the second nanostructure, the first work function metal filling a region between the first portion of the high-k gate dielectric and the second portion of the high-k gate dielectric; and a tungsten layer over the first work function metal, the tungsten layer being free of fluorine.

公开(公告)号：US11923432B2

公开(公告)日：2024-03-05

申请号：US18149224

申请日：2023-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yoh-Rong Liu ,  Wen-Kai Lin ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu ,  Li-Chi Yu ,  Sen-Hong Syue

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66553 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78696

Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.

公开(公告)号：US11923414B2

公开(公告)日：2024-03-05

申请号：US17841217

申请日：2022-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Ji-Cheng Chen ,  Chi On Chui

IPC: H01L29/06 ,  H01L21/02

CPC classification number: H01L29/0673 ,  H01L21/02631

Abstract: A method of forming semiconductor devices having improved work function layers and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes depositing a gate dielectric layer on a channel region over a semiconductor substrate; depositing a first p-type work function metal on the gate dielectric layer; performing an oxygen treatment on the first p-type work function metal; and after performing the oxygen treatment, depositing a second p-type work function metal on the first p-type work function metal.

公开(公告)号：US11915979B2

公开(公告)日：2024-02-27

申请号：US17869326

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei Ying Lai ,  Chia-Wei Hsu ,  Cheng-Hao Hou ,  Xiong-Fei Yu ,  Chi On Chui

IPC: H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L29/41791 ,  H01L29/6681 ,  H01L29/785

Abstract: A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.

公开(公告)号：US20240063061A1

公开(公告)日：2024-02-22

申请号：US18499650

申请日：2023-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Han Tsai ,  Chung-Chiang Wu ,  Cheng-Lung Hung ,  Weng Chang ,  Chi On Chui

IPC: H01L21/8234 ,  H01L21/28 ,  H01L27/088 ,  H01L29/49

CPC classification number: H01L21/82345 ,  H01L21/28088 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/4966

Abstract: A method includes forming a gate dielectric on a semiconductor region, depositing a work-function layer over the gate dielectric, depositing a silicon layer over the work-function layer, and depositing a glue layer over the silicon layer. The work-function layer, the silicon layer, and the glue layer are in-situ deposited. The method further includes depositing a filling-metal over the glue layer; and performing a planarization process, wherein remaining portions of the glue layer, the silicon layer, and the work-function layer form portions of a gate electrode.

公开(公告)号：US11901450B2

公开(公告)日：2024-02-13

申请号：US17362317

申请日：2021-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Ziwei Fang ,  Bo-Feng Young ,  Chi On Chui ,  Chih-Yu Chang ,  Huang-Lin Chao

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L29/78391 ,  H01L21/0234 ,  H01L21/02181 ,  H01L21/02356 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/66795 ,  H01L29/7851

Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.

公开(公告)号：US11901411B2

公开(公告)日：2024-02-13

申请号：US17869414

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795

Abstract: An embodiment is a semiconductor device including a first channel region over a semiconductor substrate, a second channel region over the first channel region, a first gate stack over the semiconductor substrate and surrounding the first channel region and the second channel region, a first inner spacer extending from the first channel region to the second channel region and along a sidewall of the first gate stack, a second inner spacer extending from the first channel region to the second channel region and along a sidewall of the first inner spacer, the second inner spacer having a different material composition than the first inner spacer, and a first source/drain region adjacent the first channel region, the second channel region, and the second inner spacer, the first and second inner spacers being between the first gate stack and the first source/drain region.

公开(公告)号：US20240021697A1

公开(公告)日：2024-01-18

申请号：US18366073

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L29/49 ,  H01L21/285 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/4966 ,  H01L21/28556 ,  H01L29/66545 ,  H01L29/401

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate stack over an active region of a substrate. The gate stack includes a gate dielectric layer and a first work function layer over the gate dielectric layer. The first work function layer includes a plurality of first layers and a plurality of second layers arranged in an alternating manner over the gate dielectric layer. The plurality of first layers include a first material. The plurality of second layers include a second material different from the first material.

公开(公告)号：US20240021680A1

公开(公告)日：2024-01-18

申请号：US18446681

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L21/28 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/786

CPC classification number: H01L29/401 ,  H01L29/66545 ,  H01L29/42392 ,  H01L29/0665 ,  H01L29/66742 ,  H01L21/28035 ,  H01L27/088 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823462 ,  H01L21/28088 ,  H01L29/78645

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming epitaxial source/drain regions on opposite sides of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, and depositing a work-function layer over the gate dielectric layer. The work-function layer comprises a seam therein. A silicon-containing layer is deposited to fill the seam. A planarization process is performed to remove excess portions of the silicon-containing layer, the work-function layer, and the gate dielectric layer. Remaining portions of the silicon-containing layer, the work-function layer, and the gate dielectric layer form a gate stack.

公开(公告)号：US11855185B2

公开(公告)日：2023-12-26

申请号：US17198133

申请日：2021-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ju Chen ,  Chung-Ting Ko ,  Ya-Lan Chang ,  Ting-Gang Chen ,  Tai-Chun Huang ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78 ,  H01L21/02 ,  H01L21/033

CPC classification number: H01L29/66795 ,  H01L21/02178 ,  H01L21/0332 ,  H01L21/823431 ,  H01L29/0669 ,  H01L29/66636 ,  H01L29/785

Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.